# $RCSfile: WHATSNEW,v $ (InternetCad.com,Inc.) # $Date: 2004/05/24 04:14:16 $ Version 2.0.0 pre40 ======================================================================== Beta Release Mar 24, 2009 * Fixed problems with pin function definition strings. Now we always double quote the string. chi : Mar 18, 2009 * Improved installation script EZinstall.tcl. * Added -overlapping_ends_first option which replaces the erroneous -exclude_crossing_pins option. phi : Mar 10, 2009 * Now -implicit_globals is the default mode for binding Verilog positional pins. * Now the Verilog parser reorders the physical pins if a Verilog module definition is supplied. This behaviour can be turned off by using the -nomodel_redorer option to the icrread_verilog command. * Added the -sbox and -exclude_crossing_pins to facilitate clocktree routing. The -sbox or source bounding box option can also be used to increase the speed of power and ground routing. upsilon : Mar 6, 2009 * Added the -real option to icnet binding command so that we output just real pins and not pins created from fixed routing. * Updated parasitic code to handle fixed routing. * Fixed a memory leak in the placer when ports are placed in 3D. * Added -ignore_model_expr and -ignore_models options to the icread_verilog command so we can control which instances are added to the netlist. Also added the -implicit_globals option which tells the parser that power/ground global signals are not in the positional netlist. * Added the icexit_on_order_error to itranslate so that positional errors may or may not cause the problem to exit with an error. * Added debug to tell user when there is a conflict in the order between model definitions. If icexit_on_order_errr is set, we now exit the program. * Fixed an error in the Verilog translator when using a physical model. The pins in the physical model were being added in the reverse order. * First version to include NGSPICE. Integration is not complete. * Fixed problem in detail router where fixed prerouting was able to ripped up thereby defeating its purpose. Now we add prerouting even in the presence of design rule errors. Also began work on new notch filling algorithm. * Fixed problems in the row based placer with adding clusters to vertical rows. Previously, the cells were being added horizontally to vertical rows. * Added the ability to keep or throw away the initial bin packing placement in the placer with the use_initial_placement keyword. * Now limit the number of warning and error messages when outputting cells. We count the number of error messages but don't output them all but user can change the limit through the warn control system. See .wlog file for details. * Fixed problem in the translator with not generating any pins for the default feedthru when the user specifieds a layer but the layer is not a vertical/orthogonal layer. * Fixed orientation problem with side access feeds. Now properly add side access feeds when I/Os are present and need to be routed. tau : Mar 3, 2009 * Added the redundant_side_pin_feeds option to the global routers to control the removal of redundant feeds. Values may be off, max_explicit_feeds, or max_sidepin_feeds. * Now we always make sure to restore top level view of hierarchy at the end of the program. Previously, sometimes we were left in a lower level of the hierarchy due to the optimization algorithm. * Fixed a problem with the hierarchical data structure which didn't combine pins which we have both a logical and physical view. * Fixed problem in router with misalignment of via. While it wasn't causing a design rule error, it was making ugly routes. * Added point quad and dset Tcl modules to help with advanced Tcl programming. * Added -flush option to icrecord to flush statement to file. * Added the -pin option filter to icinstance binding command and added the -filter option to icinstance get command. * Added the icdesign_name and icread_routing command to the igp floorplanner. * Added the capture_exec_cmd so we can capture the screen from a script. sigma : Feb 24, 2009 * Improved floorplanner support of clustered constraints. * Added ability of floorplanner to read detail routing in addition to prerouting. * Added environmental control of memory manager on Linux 32 bit machines. rho : Feb 21, 2009 * Test version. pi : Feb 19, 2009 * Removed double counting of feedthrus when adding side access feedthrus. * Fixed row equalization when side access feedthrus are present. * Removed a debug statement which output an incorrect ERROR message in the Verilog parser of the translator. omicron : Feb 17, 2009 * Improved the initialization and behaviour of the igp floorplanner. Now the initial placement is free of overlaps. Also the initial placement now has properly placed ports. * Fixed problem with simplify not passing initial fixed constraints to the placer. This was causing the cost_only option in the placer not to work properly. Instead of calculating the cost of the initial placement, it was calculating the cost of a bin packed placement. xi : Feb 12, 2009 * Fixed syntax error which was reported erroneously. * Fixed problems with binding errors in the Verilog parser when positional parsing is employed. * Added debug mechanism for displaying initial configuration. * Added more debug information to icread_spef command. nu : Feb 10, 2009 * Support for side pin access when clusters are present. Does not work for hierarchical clusters yet. It will in upcoming version. mu : Feb 6, 2009 * Added missing code to the net TYPE mechanism. Now the net type is output to the constraint file if it is defined. Also output the created net attribute if it is et in the translator. * Fixed a major problem in the placer with port (aka switch) optimization when timing constraints are present. Timing constraints cost function was missing an assignment and this caused the cost function to evaluate true regardless of wire length. * Fixed a crash in the global router due to an improperly freed feedthru associated with a spacer cell. lambda : Feb 5, 2009 * Added code to enable the debug of side access pins in the global routers. * Fixed problem with detail router not obeying the PIN_LOGICAL attribute. * Added the -include_models and -exclude_model options for the translator command icwrite_placement. This allows us to easily sift out unwanted models such as feedthrus. * Fixed crash when icmake_default_feedthru is placed before a physical library is read. Now it may occur first. * Improved the VHDL writer in the translator. Added -ignore_ports, -implicit_global, -ignore_layout and -no_components options to the Tcl command. * Now SPEF reader has mechanism to expand nodes when cross referencing replacement gates. * When writing SPEF we output the components in sorted order. * Added the -absolute, -raw, and -database options to icmodel pin command. kappa : Feb 2, 2009 * Improved side pin access capability of the global router. * Improved the handling of bus nets. Added the icnet bus Tcl command to manipulate bus nets. * Added support for x and y path weighting factors for length constraints. Previously this was only available for the other timing constraints. * Added ability to add a header and trailer to DSPF output files. * Added icwrite_verilog spef command in order to output SPEF strings according to the proper escape SPEF sequences. * Added ability for icconstraint Tcl to handle PATH constraints. * Fixed problems with the -literal option in the Verilog parser. * Fixed problems with the icnet rename command when [] are present. iota : Jan 27, 2009 * Added side_pin_access_file support to the global routers to allow user to specify side pin access. * Fixed crash in detail router parasitic extraction code. theta : Jan 21, 2009 * Fixed problems with a crash in the placer when standard cells are modeled as fixed hardcells. * Now parasitic analysis code is common between the detail router and the translator. In addition, the SPEF data structure is now consistent with the DSPF data structures. * Added icdesign init function so we can create a design from scratch, that is, without reading any files in the translator. * Added the -pintype option to the icmodel addpin command and added the -capacitance option to the icmodel addport command in the translator. * Restored the ability of the Verilog reader to create a dummy library if models aren't supplied. eta : Dec 31, 2008 * Added the global net TYPE constraint to the constraint file so user can designate power and ground nets. Added ability to script this in the translator using the icnet globalbind -type command. * Added a few more Tcl commands: icinstance basename, join, and parent commands. Also added icmodel instances -netfilter option. * Added the icrows::get_design_rows so one can get the number of rows in a previous run during ECO flows. * Added the icflatten_netlist -iref Tcl functions so one can explore a hierarchical netlist. zeta : Dec 19, 2008 * Added BUSBIT attribute to library pin and _BUSBIT_ attribute to circuit file to annotate the pins of busses. In addition, module I/O list is now in same order as input Verilog. * Now iroute calls idetailer in parasitic graphics mode when not in parallel display mode. Now user can gain graphics control of the detail router when iroute is called from a flow (in single processor mode). * Now icvias add command can take multiple cut geometries. Previously, it was erroneously limited to one cut. * Added the -inst option to the icmodel instances command for convenience. * Fixed a problem with min area design rule in the gridless router. More work still needs to be done. * Now we don't write out layout cells by default when writing Verilog. * Added the ability to perform filtering when manipulating constraint files in the icconstraint Tcl module. epsilon : Dec 9, 2008 * Added ability to show/hide fixed cells in the translator. * Added the depth option to icplacepads::beautify command so we can get better results. delta : Dec 4, 2008 * More improvement to vertical row placement. Fixed overlap problems for all overlap modes including gate array. Now default gate_array overlap mode is allow_space since it makes the most sense. gamma : Dec 2, 2008 * More changes to make vertically oriented rows run more quickly and with better results. The execution time is now related to number of moveable cells rather than total number of cells. * Added the allow_uneven_rows parameter to the placer. beta : Nov 28, 2008 * Fix for overlap of double height cells in the placer. alpha : Nov 26, 2008 * Added a more sophisticated row extension algorithm in the overlap routines. Now standard cell macros should map to the correct rows. * Fixed logic mistake with ignore_keepouts parameter in the floorplanners. * Made core macro transparent when model_fixed_rows and cover_cell_transparent are enabled. * Added test to floorplanners to see if overlapping double height rows are present and output appropriate output error messages. * Fixed crash in placer when double row definitions are not consistent. z : Nov 20, 2008 * Now row adaption supports vertical rows for completeness. * Fixed gate array option for vertical rows. In addition, spacers can be added to these vertical rows properly. * Added ability to simplify DSPF to a simple lumped circuit if desired. * Moved icmodel foreign command to general and common icmodel commands. * Now all Tcl-based programs have access to this command. * Added icfix_instance and icrow overlap commands to iroute program. y : Nov 8, 2008 * Now Verilog reader check to see if instance model has been defined in a hierarchical model when reading in a netlist. * Added the -simplify and -nets options to icparastics::write_dspf command. * Updated icspice::write command so that it outputs Spice subcircuit in proper model order. * Added the icmodel nets command for completeness. * Now icnets::driver_check looks for floating inputs on gates. * Fixed a problem with an infinite loop in the placer due to a bug in the implementation of split row double height cell code. * Fixed problems with complex double height rows. Code was rewritten to insure that complex cases are handled properly. * Now accept STDCELL as a valid alternative to STANDARD in the .lib file. x : Nov 5, 2008 * Added the icmodel instance -delete command. * More improvements and checks to the genrows algorithm. This includes a fix to scaling of rows. v : Oct 31, 2008 * Now we handle user defined overlapping rows much more gracefully in the floorplanner instead of seemingly entering an infinite loop. Now we output a much more meaningful error message after we have tried for some time to remove overlaps. This can happen when the user row definitions are hopelessly wrong. * Improved exact pad placement algorithm. * Improved the icrow Tcl command and added icrow add subcommand. * Fixed a problem in the clustering program where the netlist impropely wrote out a hierarchical netlist. * Improved the behavior of the pad placement code in the detail router as we now properly ignore cover cells during pad placement. * Added Draw Cell Type to ifp. Add tile info command for parasitic mode in translator. Added All Models On/Off to the standard cell placer GUI. * Added ictrace::report_models and ictrace::replace_models in order to perform crude model sizing. Added -maxlen option to DSPF generation and now default width is 80 chars wide. * Added modeling of fixed row data in floorplanner (keepout regions are still incomplete. * Began work on a DSPF parser which will read in and display a DSPF file. This included the new icread_dspf function in the translator. * Now we properly 2 point output rectangles when writing dummy models in the translator command icwrite_gds2. * Fixed problem with reading Synopsys library files. Previously, errors were generated stating that it didn't understand timing type. Improved the output error message as well. * Added the -msb_to_lsb option to icwrite_verilog so we can change order of array bits. * Added the icmodel modifypin command so we can modify a pin. Added accompanying command icpin modport command so we can alter port properties and geometries in the translator. * Added icwrite_verilog module_context function. * Improved parasitic extraction such that sliver regions are minimized. * Fixed problem with wrong endianess in processing assignment statements. This was a major problem and caused LVS errors. * Avoid crash in row-based placer even in cases where row definitions are invalid. Improved running time behaviour of row-based placer when only vertical rows are present. u : Oct 9, 2008 * Added max_classes parameter in order to control the number of classes available. * Added precision_row_control option to constrain row lengths to very tight tolerances. * Began work on incorporating 45 support in detail router. * Rewrote the icgds begin_conversion and icgds end_conversion command so that layer names can be processed properly as initialization will be performed. t : Sep 30, 2008 * Fixed problem with detail router crash when global net is not properly defined and number of ports is much greater than 2. * More improvements to lonely via processing. s : Sep 27, 2008 * Added the max_width option to the global routers. This new feature allows the user to constrain the width during area minimization. Added documentation for this feature to EZ and fixed mistake in feed_search documentation. r : Sep 26, 2008 * Fixed problem with design rule errors in mesh network when prerouting has bends in distribution trunk. * Fixed problem with missing feedthru processing which caused crash in global router when only one feed port was presented by user in library file. * Improved the ability to place relative pads in the I/O editor. Now code moves pads if they are on the wrong side and are relative. * Improved update of pad information in the I/O editor GUI. * Added the -transfer option to the icrestore_hierarchy command so we can propagate any modifications made to the flat netlist into the hierarchical netlist. q : Sep 15, 2008 * Fixed a logic problem in the memory allocation of the power and ground network. The fix results in a major improvement in memory usage when large power and ground networks are present. * Fixed two design rule errors with respect to samenet via processing. Previously, some stacked vias were not properly stacked resulting in samenet and notch design rule errors. * Improved lonely via code. Now post processing is done automatically. * Added the -nolonely option to the icoutput command in the detail router. * Added the iclonelyvia command to the detail router to allow processing at any time. p : Sep 12, 2008 * Fixed a crash in the global router when the number of ports associated with a pin becomes very large. * Added the ability to control model type drawing in the global router. * Added the ability to sort by number of pins on a net in the itools routing statistics tool in the translator. Fixed problems with scaling length. * Fixed crash in detail router when global net is not defined properly. * Fixed problem in translator parasitic code when generating DSPF and the pin has electrically equivalent pins. Previously, it was errorneously complaining that the net wasn't connected. o : Sep 9, 2008 * Fix of detail router which caused an infinite loop during prerouting. * Fixed a problem which left some nodes of the parasitic graph without an edge. n : Sep 7, 2008 * Major rewrite of timing code. This was necessary to insure complete consistency with Synopsys. * Added support for lonely via design rules. * Added full support for spacing tables. Previously, they existed internally but now uses have full access to them thru the translator. * Added ability to control output of timing table types to itools library format. * Added support for CLOCK pin attribute in the itools library. * Added Tcl stack package module icstack. * Added initial support for SDF condition statements in timing tables. * Added a trace tool and a routing statistics gui tool to the parasitics context in the translator. * Fixed LEF translator bug which translated TRI state outputs to bidirectional type instead of output type. * Now we support Verilog with empty port bindings. In addition, we also support assignments to 0 and 1 (in addition to 1'b0 and 1'b1. * Added the -replace_flattened and -flat_instance so we can manipulate the output of netlists during translation. Also added the Tcl command icnets::dump_instance_bindings. In addition, added the icrestore_hierarchy command. These options and commands allow one to restore hierarchy to the Verilog after place and route and the netlist has been modified (for example, due to scan chain reordering and buffering). Unfortunately, it is nontrivial to script. * Updated the icmodel get command so that the new -all switch returns all models including hierarchical ones. * Added error checking for the -header option to icread_verilog command. Now the command outputs an error message which the proper module name is not suplied. m : July 30, 2008 * Fix for global router port error. Global router was outputting erroneous error messages. l : July 23, 2008 * Researchers version. Updated spice.tcl. Added icdesign_name to iplacesc. k : July 18, 2008 * Fixed problem with 3d ports/switches not being placed properly. This failure occured when there wasn't any conflict between the switches and the cell library. The code erroneously thought there was nothing to do. * Improved the 3d port placement result when the core is small compared to the average cell width. j : July 17, 2008 * Fixed problem with version 40i not building properly. That version has been removed. * Improved the icbeautify command so that it removes artifacts when ripup depth is greater than 0. * Updated the EZ documentation so that prerouting is documentation is up to date. i : July 15, 2008 * Added missing code to implement cell gridding throughout itools. Gridding is specified in the parameter file. A new option called gridto allows the user to set the cell reference. The gridto may be either center, lowerleft or foreign_offset. Pad placement was augmented to grid in both directions. * Added the ability to draw vias in the translator as a convenience function. * Improved the behavior of the compactor when encountering difficult compaction problems. * Improved the 3d port/switch placer by modifying the annealing schedule. * Fixed 1 of 3 problems with icbeautify. The remaining will be fixed in next rev. h : June 24, 2008 * Modified EZinstall so that it checks to see if csh exists. If it doesn't exist, then it attempts to complete with the Bourne or Bash shell. * Added support for ignoring `ifdef definitions in Verilog. * Fixed a few minor problem in the gridded router when running on the Sun. g : June 5, 2008 * Fixed another crash with the clustering constraints. This crash occured in the translator. f : June 5, 2008 * Fixed a major problem with clustering constraints. We now avoid a crash in the clustering program when cluster instances are missing. * Added ability to draw clusters in the placer. Use Highlite Clusters option under the Edit Menu. * Added initial support for abort_subprocess parameter for debugging placement program. e : June 5, 2008 * Fixed problem with aspect ratios not being properly propagated in constraint files. Also added verbose debugging to syntax checker. * Added the iccreate_abstractions design command to build an routing abstraction to be used at the next level when itools is used to build blocks. d : May 29, 2008 * First cut of the detail router script editor. Still needs work to improve look and has not yet been put in the default GUI configuration. * Improved the performance of generating a statistical report in the detail router. * Improved the information of icnets::distribution to include number of nets and pins present. * Added the CLUSTER SUPPLY constraint so one can define multiple power supplies in an alternate way. This method is an alternate method from PARTITION_SUPPLIES. PARTITION_SUPPLIES works based on the supply nets bound to instance. The CLUSTER defines the set of instances in a power supply object. * In the cluster program, we now alert the user when rows haven't been defined. Also improved the robustness when clusters are present. Fixed problem with class constraints not being obeyed. * Now buffer synthesis code can run without timing data if the new parameter buffer_timing is turned off in the parameter file. * Improved speed of table output for large Tcl print tables. c : May 12, 2008 * Added ez:close_connections so we shutdown open process ids if EZ is shut abruptly. This prevents run on programs. * Fixed problems with notch filling when netlist is uncontracted. The notch filler was converting the entire mega net into the first net segment index. This resulted in the disconnection of the net - a major problem. * Now support multiple timing delay records with different unate properties. This was necessary to support exclusive or gates properly. * Now we test the license server in the translator when doing prerouting so the user will know if there is a problem with the license server. * Fixed problem with clock spine configuration when in flat placement mode. Now we draw the clock spine better in the placer. * Fixed a minor problem reading Spice data. Added the -tieoff_lo and -tieoff_hi options to the Verilog translator to aid when file uses 1'b0 and 1'b1 to tie off gates. * Added the icmodel instances -nets switch so we can list the hierarchical models from Tcl. * Added the out of order switch to the icread_verilog command so that the user is not required to add Verilog in the defined before referenced order. * Added icpin command to translator. Also now have the ability to control output section of the DEF write command. * Many improvement to EZ. Now startup initializes scripts in the proper order when starting EZ from command line. In addition, more button are smart in that they change color when data gets out of date or files do not exist. In addition, the detail router will not fire until all inputs are generated. * Now we can detect user added row straps during power and ground construction. This allows use to add row straps and make use of them properly when we build a power ring or stripes. * Fixed major problem reading routing constraints. All previous pre40 versions had a bug which prevented reading of the region routing. * Added experimental full chip routing compaction to the detail router. Still needs more work but the initial results are promising. This compaction is similar to region compaction algorithm. * Added the iclex -strip_comments command so we can efficiently strip C, C++, and shell comments from a file. * Improved the graphics zoom function so that large zoom out factors work properly. * Added the -g graphics switch to twflow to make things consistent with itranslate. * Now reassign limit may be zero in the global router. It was erroneously limited to one previously. * Improved the output of the constraint reader when in echo mode. * In the translator, we now draw the outline properly for ports. Previously, fill was turned on when outline was requested. * Improved the icread_cons -filter function and added the -match option to support both positive and negative logic. The improve functionality was necessary to improve EZ. * Added the -wires_to_pin option to the icread_lef command which treats obstructions connected to a pin as wires and traces them so they become part of the pin itself. b : Mar 24, 2008 * Now we support name lists in Synopsys liberty files. Previously, this was parsed erroneously. * Updated the DSPF code so that it no longer longer requires the graphical mode. * Updated the gridless router so that it can even fix connections to pins which don't meet the minarea design rule. The gridded router still follows the assumption that pins meet the minarea design rule. * Began work on generating formatted static timing analyzer reports. This work will be completed in next revision. * Updated translator abstraction Tcl so that it now supports the -enumerate switch when using the simple_only switch to icabstract command. * Added the itools_table Tcl module so we can output a formatted ASCII table. This was useful module to create static timing analysis reports. * Added the icsta clock command in the translator to facilliate proper operation of sequential circuits. * Added better error messages when flattening instances. Now we report offending instance where possible. * Now we calculate the default min pad spacing by analyziing the pad models. Previously, the default was 0 but often this would cause design rule errors during routing. The user can still set the value explicitly but now the default avoids problems downstream. * Rewrote the CLOCK constraint to work with the static timing analyzer. * Fixed a repainting problem with the contour detail router. In some cases, routes weren't completed due to missing data. While the router would eventually the nets properly, this problem slowed convergence of the routing. * Now we don't report via coverage errors of pins when pin errors are turned off. This makes the via coverage rule consistent with other rules. * Added NMOS and PMOS models to the list of models whose placement can be fixed. * Added the -45 and -all_angles options to the icpickpath routine. * Rewrote the 45 degree drawing and intersection code so that GDS2 with 45 degree angles are properly drawn and translated. * Updated icread_lef option -remove_pin_obs so that it now is more careful in removing keepouts around pins. a : Feb 23, 2008 * Rewrite of the icread_synopsys command so we can correctly parse the Synopsys library format. The static timing analyzer was improved and now gives the correct answer for combinatorial circuits. Sequential constraints will be fixed in an upcoming version. * Updated DEF so it reads pin properties correctly. * Now we can control the precision of the libraries delay data from the translator with the icwrite_lib precision command. * Fixed problems with padgroup constraints in the iroute program. * Added icinstance remove_type command to remove filler cells. * Improved the ezredir Perl script to automatically create a backup file. * Improved EZ documentation system so that it cleans files properly with the new itoolsdata structure. Now allow translation of multiple GDS2 files in EZ. * Fixed msg initialization problem in placepads::check_overlap. Version 2.0.0 pre39 ======================================================================== : Feb 14, 2008 - code freeze version 2.0.0pre39. Now in beta directory. y : Feb 6, 2008 Added cluster_priority keyword to the placer. This allows the user to either allow clusters or fixed constraints to dominate when both refer to the same instance. The default is for fixed constraints to dominate, that is, clusters will be ignored for any instanced that has a non-trivial fixed constraint. A trivial fixed constraint is an initially fixed constraint. Fixed a problem with compact_cell overlap algorithm which did not proper set the starting position on a manufacturing grid. Updated icobstacle::grid_point idetailer Tcl so that we check to make sure that a grid is defined before attempting to grid coordinate. Updated iccost_state:save command in the detailer router so that missing cost components are all now saved. Added missing gridding to the iroute program. x : January 31, 2008 Fixed a problem with incorrect output of the new cluster splitting code. Previously split clusters had random output. w : January 31, 2008 Fixed a crash in the the new cluster splitting code. It happened when the clustered cell has orientation 2 or 3. Updated the scan code to make the output net name correct if at all possible. v : January 22, 2008 Now we automatically split clusters which are longer than the length of the into two pieces. Now we properly reference Verilog models with leading backslash to the cannonical form found in the library with leading backslash stripped. Fixed problem with outputting the wrong pin name when generating DSPF. Fixed several netlist writers so that they handle multiply bound pins (must connects) properly. Previously, they worked but output annoying false error messages. They include the def writing in the translator and iroute. Added the DISTRIBUTE_MODEL option to the buffered net H-tree algorithm. This will allow the user to supply any driver model to the center distribution driver including a null driver cell which just provides routing. Fixed "ERROR[ADD2SET]:value of node is out of bounds of set" problem which was due to a row class assignment problem. Added the iclicense::available command so you can stop a program if the license server is not available. Added ability to draw standard rows in the translator. Improved and fixed the icswap_coordinates function so that it now properly orients routing and pads. Added the -toplevel option to the icwrite_def command for completeness. We now keep track of vector wires when outputting Verilog. Added icinstance remove_spacers to support gate_arrays properly. Fixed problems with icmodel boundary command when modifying the boundary. Offset was not properly calculated. Fixed problem of moving rows when no cells are present in a row when in gate array mode. The program iroute was modified to fix the problem. Fixed problem with crash when manually added routing in the idetailer program. Added the icscanpath command so we could draw scanpaths in global routers. u : January 22, 2008 Added more debug to the Verilog translator so that it gives better error messages when binding mismatches occur. Also fixed a problem binding Verilog signals when two leaf instances have bus signals. t : January 17, 2008 Added the icwrite_verilog dictionary commands which create and maintain a dictionary of all identifiers where all special characters that normally need to be escaped in Verilog will be replaced with the underscore character. The facility will maintain a 1-to-1 mapping between the itools cannonical names and the modified names so that no shorts or opens are created and that an inverse operation is possible. The Verilog writer, the Spice parasitic routines (including DSPF) and the SDF writer all now automatically adjust their output if the dictionary command is present. Fixed problem with hierarchical foreign offsets. Previously, the foreign model offset was not applied properly. Added the -antenna option to list antenna attributes when displaying bound net pins for the icnet binding command. s : January 11, 2008 New hierarchical pin optimiziation algorithm has been added to the igp floorplanner. Eventually, this floorplanner will be extended to allow full hierarchical placement. Also added the cover_cell_transparent option to allow different defintitions for the cover cell. Added a missing function in the itranslate program which will allow the icalert_user dialog box to work properly. Also added the -graphics switch to the icalert_user dialog box so that it can start the graphics system if needed. Otherwise, it just sends the message to the defined message system. Added the icplacepads::check_overlap command in the translator so we can check user data when exact pads are present. r : January 9, 2008 Improved the behavior of the strap router. Now vias are properly array and now the router makes use of generated vias if such information is available. Fixed a bug where hierarchical models were not output in the translator. This resulted in syntax errors. In addition, fixed a crash when an expression was present in the Verilog. Added the parasitics graphics context in the translator to facilitate the generation of DSPF (Detailed Standard Parasitics Format). While simple combinatorial cases work properly, more complex circuits are not output correctly yet. This will be fixed in a future version. This was implemented by the new icnet parasitics -graph command. Fixed a problem in the iroute program which prevented the proper transfer of antenna rule information such as gate and diffusion area. Added the icinstance isa_io Tcl command so we can properly discover itools generated IOs when writing foreign netlists such as Verilog. In addition, the icinstance bind command now properly outputs globally bound signal pins. Fixed problem with missing commands when starting graphics from a script when the program was not started with graphics. q : January 4, 2008 Added the _ICASSIGN_ statement to the itools circuit description. This was added so that scan paths can correctly constructed and be correctly described in Verilog. The scan path algorithm was augmented accordingly. The assignment was necessary when IO pads connect to intermediate points in the scan chain. The resultant scan chain could have two IOs on the same net which would require an assignment statement. p : January 1, 2008 Fixed a design rule error (samenet stacked via rules) in the gridless detail router. This was due to the path straightening code which aligned stacked vias. Now we supoprt the -implicit_globals switch in icwrite_verilog command. In addition, we now no longer write globally connected pins into the netlist when icglobal_nets is false. Previously, some globally connected pins were output. o : December 30, 2007 Fixed problem with crash in new strap router in the detail router. Also added the ability to draw cell types in the detail router. n : December 28, 2007 Added the icstrap command to the detail router. This command straps two adjacent layers together with vias. It was added to facilitate the generation of power and ground networks thru Tcl scripts. Added minimum height discriminator to the power mesh code in order to be consistent and flexible. Modified the stripe code to automatically connect multiple global pins. Added the -noiclib option to the icwrite_lib switch so we can make a cover cell include file. m : December 24, 2007 Now the floorplanner properly places unconnected pins on the edges of the soft macro cell. Previously, it was erroneously putting them at the center of the cell on top of one another. Now static timing analyzer understands so that it understand multiple I/O pins connected to the same signal. Fixed problem in iopad cell generator which was causing a small design rule error due to manufacturing grid. Added the icmodel pobject command so that the user can properly connect and select multiple pins with the same pin name in the Tcl interface. Fixed a bug in the icmodel addport command which prevented the proper coordinates from being entered. Added the -allow_empty switch to the Verilog parser in order to accept an empty Verilog structure, that is contain no instances. Ordinarily, this would be an error but this is useful for testing and creating the itools I/O interface. Rewrote the escape mechanism in SDF and Verilog writing routines so it properly matches the Spec and the EZ documentation. Updated so that cover cells are properly ignored during pad placement. This allows the overlay cell to exceed the pad placement area. Fixed a problem with relative pads in which the coordinates were not properly set. Ran into the biggest weakness of Tcl - the need for an expand function which is currently in Tcl 8.5 and not in the current used by itools stable 8.4. Now we could upgrade but they still haven't made up their mind on the finality of the expand function syntax. To get around this we added a workaround for the parts of lists that need to be doubly braced so the list remains valid when eval strips away one level of braces is removed. This function is called the icadjust function and now is available to all Tcl programs. Added support for modifying labels and added the structure rename command in the GDS2 translator code. Also now support drawing of a particular model type in design mode. Improved behaviour of static timing analyzer. Added ability to modify loads at internal nodes thru Tcl for testing purposes. Updated scan discover command so that it works with cover cells. l : December 14, 2007 Now the generated buffer cell instances use _ instead of : in their names so they don't create an SDF conflict. Added the convert_cover_to_pad_pins Tcl script to change cover cells to pads when necessary. Added the ::icplacepads::pad_pins function to the translator for convenience. Added icvar_set and icvar_unset in order to make user scripts more readable. Rewrote routing attributes so we can support more attributes to prerouting. Now we support the FLEXIBLE attribute which will be used for rubberbanding wires. Began support for generating VIA rules. Not complete. Improved the PIN IGNORE constraint implementation. Now it is used to ignore pad connections (when requested) and to improve the scan chain optimization. Added the icmodel pin -foreign option for completeness and convenience. Improved graphics display in iroute. Now the net order command in the detail router takes a port argument to allow unambiguous connections. Improved support for pattern vias in detail router. Pattern vias can now be used in scripts to construct power and ground networks. The translator can now describe and manipulate the pattern vias. k : December 8, 2007 Added the ::icmesh::build_flexible_mesh command to automatically extract power and ground mesh and prepare it for routing. Fixed problems with retain replacement policy. This bug was introduced in version 39i. It caused the introduction of double geometries which eventually crashed the global route after thousands of errors. Added icreplacement_policy all to make it easier for the user in the common case. Improved on the write verilog command. Now it automatically recognizes the itools port/pads which are added automatically to a verilog netlist. Added the icnet intersect function in the detail router so we can automatically build a flexible power and ground mesh network. Added ability to control drawing the various cell types in iplacesc and igp. Eventually, this code will be migrated to all programs. j : December 3, 2007 Added the ability of the gridless detail router to route pin-to-pin connects in a manner which will be suitable for simulataneous routing of signal and power nets. This should be a big win in terms of area. The finished version will be in the next version. The user can now control the connections of pins with the icnet order command. Fixed problems with prerouting model in global routers. Added ability to draw axis, core ring, and pad rings to placer, floorplanner, and translate programs. Fixed problems with PAD_ALIGN constraint. Now we can change setting for the translator and we fixed typo problem that caused syntax failure. Fixed translation problem with multiple cut layers of a via. Previously, they were incorrectly lumped into a single geometry. Fixed design rule problem with asymmetric vias. Internally, the vias were placed correctly. They were just output at the incorrect coordinates. Added path support to itools edit objects. This was done to support the manual creation of centerline paths in the detail router. Updated itools flattener to properly expand any bus definitions in models below the flattened level. This is to facilitate proper hierarchical optimization during floorplanning. Updated the Power and Ground Network documentation in EZ to reflect the capabilities of the tools. Now both cell-based and primitive-based mesh networks are supported. i : November 30, 2007 Fixed translate problem with icgds_define command and nimplant layers. Added ability to dump a set of models to the icwrite_lib and icwrite_lef commands. Added the icreplacement_policy foreign command for completeness. Fixed the icreplacement_policy keepout merge command which was improperly coded. Fixed the icreorigin translate center command. Added the icrule SPACING LOOKUP command. Aded iclayers manufacturing_grid commands as well as iclayers up and iclayers down, icvias routing_layers, icvias default_up, and icvias default_down. These commands were added to facilitate the ability to generate a power and ground mesh cell from the feed/fillcell definition. Now we check to see if the global nets have the CREATE flag associated with the net. Also added the icnet create Tcl command. h : November 23, 2007 Added the icconstraints::instantiate_model for convenience. The function allows a model to be instantiated and placed at a given coordinate. Improved igp floorplanner graphics so that it can display hierarchy properly. Now we output all of the coordinates of a hard pin on a soft macro cell. Previously, only the first point was output. Updated the model instance placement code so that all coordinates are relative to the center of the cell. This makes everything consistent. In addition, we fixed a problem with erroneously truncating the model instance list when an instance appears in circuit description but not in the physical description as a fixed entity. Now we build and maintain scanpaths in order. Previously, the order could reverse which makes things confusing. In addition, the .scan file is now a valid constraint which can be read into itools using icread_cons and display the path graphically. We added the ::icscanpath::display command to the itranslate GUI. Added the icinstance pin_netid command for completeness. Fixed problems with icsizer bloat_shrink procedure. Subtraction order was mistakenly reversed. Fixed problem with cut keepout violations occuring over virtual keepins in the region router. Fixed problem in generating the PRESENTATION record in GDS2. g : November 19, 2007 Fixed problems with the translator not outputting correct netlist when in hierarchical mode. Fixed a problem when calculating the proper foreign offset also when in hierarchical mode. Updated icextract_fix_model_instances so that it only changes the type of the fixed constraint if such a constraint has already been generated. Fixed problems with the syntax of the SDF file when in the static timing analysis mode. This mistake was introduced as a new feature in version 39f. Added the ability to program the version and generations of the output GDS2. Rewrote the scanpath code in the translator so that it now supports the icscanpath complex command. This allows one to describe multiple gate scan paths definitions. We also added the findpairs subcommand so we can find all of the available scanpair paths automatically. Now the translator command icwrite_verilog supports a filter function and a header rewrite function. The user has complete control of the rewrite of instance, model, and net names. In addition, we added the -header option to the icread_verilog command so we can write out the top level Verilog definition. Fixed problem with Synopsys function parser in the translator. f : November 11, 2007 Added a new cell origin option to the fixed constraint definition. This option allows one to use foreign origins directly. Now it is easy to convert to Cadence since you can use the Cadence coordinates directly. We added support for system timing checks in the Verilog. Strictly speaking this should occur in structural Verilog but it now may occur. Itools will simply parse it and ignore it. In addition, we added support for special case of net binding. More work on creating proper SDF data. Now we output setup and hold constraints into the SDF. e : October 29, 2007 Now we allow empty string hierarchy divider characters for more flexibility. Fixed crash when calling the itranslate icgds help function. Fixed problem with calculating GDS2 foreign offsets when bloated data changes the MCR boundary area. Added the ::icvirtuoso::define_global_nets function so now the user can remap global names to Cadence global names. Added missing trigger edge keyword to setup and hold time definitions to be consistent with Synopsys Liberty definitions and to support SDF timing checks. Now translator can read multiple Liberty files and generate min/max SDF timing delays. d : October 29, 2007 Fixed problems with extracting GDS2 prerouting data from a structure. Now icextract_prerouting will extract correct results whether the prerouting_model cell exists or not. In both cases, we will interpret the data as wires so bloating may be properly be applied. Previously, in the default case, the boundary of the prerouting cell was incorrectly calculated when no user boundary geometry was present and the MCR was used as a boundary. Added the -wire option to the icmodel add keepout command. Improved the sizer in the translator so we can do single layer operations easily. Added shrink_bloat Tcl so we can easily combine NWELL geometries in a script. It was possible previously, but this minimizes the amount of user code in a very common operation. Added the -script option to icsizer exec as a convenience to make scripts shorter. In addition, the sizer won't crash if the rules contain errors. Now the ICLAYERS keyword may occur in the input layer definitions as a convenience but with the caveat that it must be the first layer definition. This requirement is enforced by the BNF syntax. Fixed a problem in the contour detail router which prevented routing a valid stacked via configuration. Fixed a crash in the placement program that occured when model instances occur in a standard cell model. Added new features to the icsta command (static timing analyzer). We now support integration into SDF as a timing calculator. Also added the icsta dump and icsta trace commands for debugging. Added the -sta option to the icwrite_routing_sdf command so we call the static timing analyzer to calculate the delay times using Synopsys delay tables. Fixed a problem reading Synopsys library files when the function contained &. This version of the AND function was not supported previously. Now the verilog translator will look in the defined library models in order to resolve model names, specifically, the translator will look thru the list of module instances in order to determine model definition. In addition, now the Verilog translator correctly translates models with generic Verilog names such as and, or, xor, etc. The itranslate flattener will attempt to transfer any fixed constraints in the top level module to the global scope. c : October 21, 2007 Added support for arrayed vias in itools. The array construct has been documented in EZ. In addition, the cct translator now supports translation into the itools arrayed via construct. Added the viarule spacing rule in order to support arrayed vias. This has been documented in EZ. Now we use iclayers manufacturing in the Tcl power/ground ring code in order to tame the Tcl roundoff problem. Added the icsta command to the translator. This command will implement a static timing analyzer in the translator. It will borrow common code from the placement engine. The command is currently incomplete. Added the iccct orient command so one can convert between itools and CCT orientations. Fixed problems with expanding macros in Verilog. The macro expander was implemented backwards and this induced parsing errors. b : October 11, 2007 Now we support rotated vias in the prerouting data. This has been documented in EZ. Fixed problem with moving fixed ports in the placer. The problem occured while using port algorithm number 4. Improved prerouting support translation for CCT format. Now translator understands arrayed and rotated vias properly. Added support for the -exit_on_error option to the icread_spice2 command. In addition, this command has been augmented to handle multiple model file arguments. In addition, only the first data is used for a model; all other redundant data for a model is ignored. When ordered model files are present, the program now checks and reports all models which don't have reordering data. When the new -exit_on_error option is present in the icread_spice2 command, the translator will abort the run. a : October 7, 2007 Improved the unlap algorithm for cells with rigid neighborhoods especially those with many distinct neighborhoods. Added missing va_config clause to CCT wiring in itranslate. Fixed problem with crash reading Verilog with partial designs when model is not found. This bug was created in version2.0.0pre38. Fixed problem reading GDS2 data when data should be ignored. It was improperly being added to first cell which was not ignored during a multiple GDS2 file read. Only the first object of the GDS2 structure was ignored instead of all of the objects. This resulting in binding errors. Now the compactor will not be called if all cells are fixed as it just wastes time during placement. Version 2.0.0 pre38 ======================================================================== : October 4, 2007 Now properly handle multiple merged layers in the itranslate Tcl commands ::icconstraints::extract_cover_cell_neighborhoods and ::icconstraints::extract_neighborhoods_from_routing. Improved the initial neighborhood placement algorithm so more cells are placed within their neighborhoods. Updated placement prerouting code to include missing via code. Fixed user extensions in itranslate LEF code reader. Now we prevent a crash in the gridded router when routing areas near the boundary of the grid. Also fixed design error in the gridded router between routing and unconnected pins. Now support via options in the CCT .wir format. Added the icrow rowsep command to itranslate so we can calculate average row separation for the user. Augmented the Verilog reader so that it can read out of order Verilog, that is Verilog where things are referenced before they are defined. Now we tell the user when they didn't set the flow when generating the grand.do file in EZ. Now prevent tiny slivers from forming when editing the placement of instances. gamma:26 September 2007 Fixed out of order statements in placer which caused crash when port algorithm #4 is enabled in hierarchical placement mode. beta:25 September 2007 Now we check to make sure that we don't create a rigid neighborhood smaller than the width of the cell. This was occurring in the itranslate Tcl routine icconstraints::extract_neighborhoods_from_routing. We also modified the placer to remove any invalid neighborhoods which are too small for the given cell width. We improved the initialize random placement algorithm so that rigid neighborhoods were properly observed. Also fixed typo in neighborhood report. alpha:19 September 2007 Added missing -toplevel option to the icread_spice2 itranslate command. Also put WHATSNEW file in reverse chronological order for easier reading. z:18 September 2007 Now translator can draw routing, keepouts, and ports with a border for better viewing. Now we avoid error message in icwrite_routing_sdf when net is a power/ground net. Fixed problem with initialization of ports in the icread_spice2 command. Previously, both pads and ports were being output as the same entity. y:14 September 2007 In the Tcl procedure icnets::driver_check, we now include nets which are tied-off to power or ground as nets having a driver. In the translator, we added the -case_insensitive switch to the Tcl command icpin_type update for convenience. Also we now can write out netlist even if hasn't been flattened. Added -model_file capability to the icread_spice2 command and allow this command to read spice subcircuits out of order, that is, now they don't need to be defined before referenced. However, they must be defined once all Spice files are read. The icread_spice2 command also now takes the top level module as an argument when flattening of hierarchical netlist is desired. Fixed a problem with flattening netlists in that one extra level of hierachy was being added to the net name. Also we prevent a crash when one tries to flatten a null netlist (no data read in). x:12 September 2007 Fixed problem with replacing fixed instanced with rigid neighborhood constraints when using the extract_neighborhoods_from_routing. Fixed problem with icadd_keepins delete command deleting user added keepouts. Fixed problems with Yvector_alloc messages when prerouting is present. w:12 September 2007 Added the -region option to the icdesign_name command in the detail router. Fixed problems with restoring user added keepouts during region compaction. User added keepouts would dissappear during compaction. Other keepouts were not affected. v: 7 September 2007 Changed internal fixed constraint structure namely neighborhoods so that we maintain original constraint so we can visualise neighborhood constraints. Added rigid neighborhood support to the fixed instance GUI. Now we also throw away invalid neighborhood constraints when the neighborhood does not intersect a standard cell row. Fixed problem with upper right boundary of neighborhoods. They weren't getting adjusted properly. Edit cell now user to visualise the neighborhood constraints. Use the Advance button to display GUI. Now we pass prerouting to placer so we can perform proper overlap removal when we perform port placement. Previously, we didn't read prerouting into the internal database. Added the ability to draw prerouting in the placer. Updated the return Tcl list from the icfix_inst get command and added the -adjusted and -neighborform options. Added the ability to make the itranslate command icgeometry use maximally vertical tiles through the use of the -max_vert options. Fixed the icpadgroup help command in the translator. Added the icplacepads::extract_side_padgroups so we can generate padgroups from a given set of pad placements. Added the compact_ports autodetect mode which determines the port layers from the layers found in the referenced port cell models. Added merge_port_layers option to the placer so that user has control over whether all ports are placed at the same time or ports are placed on a layer by layer basis. Improved the results of 3d simulated annealing port placement aka cport algorithm #4. Fixed problem with design rule violations using this algorithm. u: 29 August 2007 Now itools automatically inherits pins from subinstances below the placement object. So in principle, the user could have subplacements with pins within standard cells. This is most useful for large complex macro cells. In addition, models no longer need to be defined before reference in the library file although it is still encouraged. However, they do all need to be defined at the end of a library definition. Fixed problem with %INCLUDE file in reading parameter files. Now translator can handle designs with no via geometries if require_vias is off. Updated graphics in itranslate so it can draw hierarchy in the model view. Now the translator can read incomplete verilog designs using the new -partial option. This is useful in floorplanning. Added the -unnamed option to the icmodel foreign command in the translator. Improved the functions to the iccrossref command in the translator. Added the -physical_only switch to the icwrite_ic command for partial netlists found in floorplanning. Added an attribute argument to the translate filter of icread_verilog so one can distinguish the usage of a string. Current values of the attribute are : instance and module. Added the the -placed and -init switch to the icmodel instances command. Added icextract_fixed_model_instances to extra model instances from a top level module. Added the icvirtuoso::hierarchy command for building Cadence compatible instance names. Fixed problems with the floorplanner when complex attributes are added to a cell such as the GROUP attribute. t: 15 August 2007 Documented the license_max_tries parameter. Added the iclicense::unavailable Tcl command and documented it in EZ. Major rewrite of the fixed data structures so we can properly handle fixed and rigidly fixed neighborhoods in hierarchical designs. Fixed error message (illegal tile) in TimberWolfSC when placing ports. Fixed problem translating CCT paths. Previously width was set to minimum width instead of reading width value suppplied. Added icconstraints::extract_neighborhoods_from_routing so we can prevent placement of cells over prerouting. This uses the new itranslate "icgeometry routing" command. s: 27 July 2007 Added the icinstance remodel command so we can swap out different models for an instance. Also added the icremodel Tcl command (which uses the icinstance remodel command) and searches the netlist and replaces any instance with the given model with a new model. r: 25 July 2007 Added the *memory_messages option to the parameter file to turn off memory usage messages which annoyed some people. Now it is optional. In addition, we added the icmemory messages command to itranslate so you can turn it off in the translator as well. Documented this in EZ. Now we allow partial synopsys libraries, that is, the library keyword is no longer mandatory. Now icread_synopsys properly reads files with DOS carriage return characters. Also error messages are improved when reading Synopsys library files. q: 23 July 2007 Fixed two infinite loops present in the placer. The first loop was due to a mistake in the cluster building algorithm. The second type of infinite loop occurred when many fixed cells were present and the valid locations to place the standard cells were few. The program was not trapped in a loop but required an inordinate amount of time to find a valid position. A new algorithm has been constructed which efficiently finds the valid placement locations. p : 16 July 2007 Added timeout debug info to Expect scripts run in debug mode. Added the iclog function to ICTk so we can redirect stderr to a log file in the icdaemon. In the parallel routing algorithm, fixed a problem in reading the process id when using the icdaemon startup mechanism. This resulted in effectively removing this host from participating in the parallel routing. Now we use the full pathname for the rout.# redirect files in parallel routing. o :12 July 2007 Removed a memory leak for the floorplanner and placer when compaction is performed. Now license taginfo cleanup command works only on the userid from the requesting stream if the requesting connection is non-privledged ladmin. In privledged mode, taginfo cleanup command will removed all tagged programs and request them to reregister. Improved countdown counter so it works properly regardless where it is on the line. Fixed default prompt for the ichost startup tool. The Expect script requires \$ not $ because it will be treated as a variable and not as a symbol. Now the ichost tool only recognizes icdaemons that the user owns and reports when a login name mismatch occurs. Now icdaemon uses countdown counter during waits for prettier output. In addition, the icdaemon now removes stale suicide files so it doesn't kill itself. Added more debug to parallel routing commands. Now the addition of a second -debug keyword enables very verbose parallel debugging. Fixed problem with license not releasing after parallel routing. n :11 July 2007 Added -hostfile argument to ichost tool so we can read a host file in for the user during automatic test of the host file. Updated syntax program so that it now supports automatic testing of the host file. Added the test of icdaemon registration so we can check the license server for correct operation. Added documentation for fix_orientation_problems in the placer. m :10 July 2007 Fixed problem with parsing hierachical netlist format. Added missing keywords to parsing table. More documentation on hierarchical netlist. l : 9 July 2007 Hierarchical netlists documented in EZ. New -nogui switch to ichost command. Better error messages added to ichost as well. More ichost and -mount option in the circuitName.host file documentation. k : 2 July 2007 Fixed a problem with a low level data structure which was causing problems with redrawing data to the screen. Fixed spacing problems with floorplanner compactor. Ports were being placed too close. Added new ability to anneal ports in the standard cell placer. Use ICSC*compact_port_algorithm : 4 in the parameter file to enable this algorithm. j :29 June 2007 Fixed a problem with overlapping cells when pedestals are present in the standard cell placer. Reorganized the netlist definition so it is consistent with the flat definition. Now the netlist is contained in the .ckt file instead of the library file. Added the -hierarchy switch to the icwrite_ckt translator command. i :16 June 2007 Added Capture Screen command to EZ GUI for completeness and utility. Improved the behaviour and features of the host tool so it works better with the icdaemon. Improved the icdaemon so that it has -restart and -suicide options. Documented the use of parallel hosts for routing in EZ. h : 8 June 2007 * Fixed crash when design does not have any nets and has cluster constraints. g : 7 June 2007 * Added icexit_on_incomplete command to the translator so one can invoke graphics log reader mechanism on a failure to complete the script. * Added the -area and -layer options to ictell_tile function in the detail router so we can get info on tile data in an area and on a given layer. f : 4 June 2007 * Fixed crash when no placeable objects exist in the standard cell placer. e :24 May 2007 * Fixed problem with spice flattener due to continuation characters and DOS files. Also fixed problem reading include files and improved spice parameters for mosfet instances. d :17 May 2007 * Added the icinstance binding -instorder command so we can output a Spice netlist from the internal netlist format. * Improvement to the icrouteable command so that it detects when a route is not possible due to missing vias in the technology section. * Added the icspice parameters command so we output a spicelist from the internal itools format. * Fixed mc_compact so that it can handle negative core coordinates. * Now iplacesc shares the compactor code from igp and so now it doesn't have to fork a process to call mc_compact (old compactor). This speeds execution time when ports are present. c : 9 May 2007 * Fixed problems with merging cover cells when multiple pins with the same name exist (must join pins). In addition, the prerouter was modified to properly handle must join pins. * Added ability to control flattening by the use of model information in addition to instance control previously added. b : 2 May 2007 * Fixed problems with the icnet command in the placer, global routers, and detail router. Some subcommands were not working properly due to a conflict introduced in the last version of 2.0.0pre37. * Added net WEIGHT option to the icconstraints Tcl namespace for completeness. Added the -copy_first option to the write_constraints function so we can reorder constraints as needed. * Now overlap errors in the placer return an error and activate the graphics log reader when exit_on_error is enabled. * Fixed a problem with scaling the spacing requirements for port placement when absolute coordinates are given. Because the compactor was given the wrong spacing values, the ports would effectively overlap. * Fixed implementation of net WEIGHT constraint so that user constraints are observed. Previously, weight constraints were only accessible/generated by the program itself. a : 25 Apr 2007 * Added the PIN IGNORE constraint so individual pins may be ignored during placement. Added the icnet routing exists function and moved the icnet routing command from the translator to the dynamic misctcl library module so all programs can issue this command. Added the icnet ignore_pins commands to provide Tcl interpreter support for the PIN ignore constraint. Version 2.0.0 pre37 ======================================================================== m :23 Apr 2007 Now we store off io_port names of CCT input so we can restore them upon the creation of a .ses file. :25 Apr 2007 beta release Fixed problems with rounding positions of virtual ports. Problem was due to unnecessary floor command in the Tcl procedure. l :19 Apr 2007 Now ictile_info of the detail router takes the -center argument to calculate and display the center of a tile. The create abstraction Tcl now takes two additional arguments: -nominjog and -targetpins. The -nominjog turns off the minjog code. The -targetpins allows a via to be placed on a pin during prerouting. This was added to improve the prerouting on some older technologies which don't have minjog rules. In addition, we now allow the y position of the prerouting to be specified in the exact order list. Also we now use a more thorough algorithm in searching for the geometry to align the pin during prerouting. Added the -create_nets/-nocreate_nets options to the CCT translator so that prerouting can be read and instantiated even if it is not in the netlist. k : 6 Apr 2007 Added the ability to output pin type and pin attributes from the icnet binding command. Improved prerouting model in placer and floorplanners so that all prerouting is screened to see if the geometries should be converted to freeways. This can radically improve the results of connections to prerouted busses. Fixed problem with initializing the number of points in a path when translating from CCT. j : 5 Apr 2007 Now standard cells fixed as hardcells can now really can take on the main attribute of hardcells - rectlinear shape. This is useful for multirow L-shaped cells. Now a better error message when reading unknown components in a SPICE deck. Now we support partitioned power supplies where the user has defined the power supplies for each row. Automatic assignment is almost complete. i :22 Mar 2007 Fixed problem with overlap of double height cells in overlap routines. This problem occurred when the user fixed a double height cell in the row and other double height cells in the row could get overlapped in the row direction. Added icnets::driver_check Tcl procedure so the user can check to see if all nets have a driver. This allows earlier detection of problems rather than waiting till later in the flow during SDF creation. h :21 Mar 2007 Fixed problem in VHDL translation which added bogus interface pins. g :20 Mar 2007 * Fixed problem of outputting error messages in the sdfwrite translator command when the net contains only a single pin. * Added support for the -supply_binding option to VHDL parsing so user can map logical 1 and 0 to the power/ground supplies. This will allow users to tieoff gates to logical 1 and 0 in the VHDL yet physically tie them off to the supplies. f :13 Mar 2007 * Fixed CCT translator to understand multiple word properties. * Fixed Synopsys translator so that it understands quoted strings much better. e : 2 Mar 2007 * Updated programs so that class constraints for clusters are inherited from the member instances. * Translator now by default creates nets that the router has generated when reading the final routing. This may occur on power and ground nets which the router may have generated. Previously, these nets were ignored. d : 22 Feb 2007 * Added the icmodel instances command to the translator so one can list the instances of a hierarchical module. Updated the icread_vhdl command so that it can take hierarchical netlists and now processes assignment statements properly. In addition, the IO pins are now added properly. Also added, -case_insensitive switch which converts names and identifiers to lower case. c : 15 Feb 2007 * Fixed problem with conflict between Draw Reference and Graphics Update command in iplacesc program. * Fixed problem with poor result with small chained test case. The move strategy code had a problem which resulted in the annealing schedule aborting early after 1 iteration. b : 08 Feb 2007 * Now we alway output a model if it is used. The translator had a logic problem which prevented this from happening when hierarchy is present. a : 07 Feb 2007 * Fixed problem with translating design names that end in _#. This was conflicting with itools names for routing regions. Now routing regions will be suffixed with _R# to lessen the conflict and additionally, the -basename switch will allow the user to override the name truncation mechanism entirely. Version 2.0.0 pre36 ======================================================================== * Fixed unitialized variable in igp which was causing errors in the global router by not initializing the position of the cells properly. * Added the model type info to the iceditcell GUI and added the ability to edit the size of softcells during floorplanning. * Now take neighborhood constraints into account when we perform initial placement. * Improved quality of the detail routing by fixing a bug in the cost calculation. * Fixed problems with error messages in the placer when class constraints are present in the hierarchical mode. * Fixed a problem in the global router which avoids a crash if pins are not defined properly or are shorted together. * Added the -boundary_depth option to icread_gds so the user can control the depth at which the translator will look for the GDS boundary. Default is one. Previously, translator looked at all levels. * Fixed problem with global router complaining about pins not being on a routing layer when in fact they are on a routing layer. * Major rewrite of the icnet command in the detail router. Now this command uses common code so it will be more reliable in the future. * Fixed misleading error message when global pins are not properly added to the design. Previous, it was stating no equivalent pins were found which is total bogus. Obviously, a copy and paste error. * Now support subcircuits at the end of SPICE files. * Row class constraints in the genrows topology program of the floorplanner is now persistent. Use the -persistent option of the icgenrows class constraint. * Added support and documentation for VALID_ORIENTS clause in fixed constraints. This will allow the user to set an individual instances valid orientation set. Previously, the set of valid orientations was set by the model. Now, one can override the model definition for individual instances. * Rewrote the Edit Row gui in the row topology generator of the floorplanners (ifp and igp) so that the class definition is persistent and alignment of supply pins considers layer. * Added save and restore capability for idetailer's cost structure. This file is called and .rcost file. These options have been added to the GUI. * Improved quality of the detailer router by eliminating some cases of slivering. In addition, improved code for aligning metal to vias which will reduce the number of DRCs for complicated routes. * Added missing iclayers command to first generation floorplanner ifp. Also added bin packing initialization code from igp to improve results. * Added a new variable pad placement algorithm based on dynamic programming which yields better results. Use *pad_new_algorithm : on in the .par file. In future releases this will be the default algorithm. * Added support for environment variable ICVERSIONCHAR which allows the user to specify the backup separator. This is needed for MS filesystems. * Rewrote icplacepads::beautify so that it is more effective. * Added support for virtual pads and ports. This was need to model Virtuoso pins more accurately. * Updated icgds find command so that it can work on a single gds layer. * Fixed problem with contracted netlists in the gridded router. * Fixed problem in the global router which erroneously assigned the positions of feedthru pins to off grid positions. The problem was in the vertical constraint minimization stage. * Updated LEF/DEF parsers so that they can read DOS file format. * Improved syntax algorithm so it does not exhibit O(n2) behavior on circuits with explicit power and ground representations. * Improved the icread_synopsys translator command so that long lines do not result in a syntax error. Now handle internal pins correctly during parsing. * Added gridding to the output_at_density option of the global router. In addition, we added the output_horizontal_layers option to control the number of horizontal layers used for the density calculation. * Improved pad placement code using linear assignment. Now both gridded and griddless router use the improved code. * Fixed problem with the icreplacement_policy keepouts replace in the translator. Previously this command had no effect. * Updated the icrecord command so that it support the -noexec switch and the -- options. The -noexec switch was needed to output the Tcl commands into the history when script generation routines are executed. * Improved the power/ground construction scripts in the detail router so that they now output the commands necessary to run the same operations in a do script. You will now find the commands in the Tcl history and .ddid file. * Added PAD_NEW_ALGORITHM option to the ncons files for convenience. * Fixed problems with removing overlap of cells in vertical rows. * Fixed problem with license server logging so that more exit points are supported with better error messages. * Fixed missing property attribute for wires in the CCT translator. * Now license server uses the /var/tmp/.itools directory to store the lock and pid files. This is to be compatible/consistent with FLEXLM and prevent cron jobs deleting these files accidently. Previously, the pid file was in /tmp. * Fixed a bad crash in the detail router due to new pad placement code. * Fixed a major problem in the placer specifically due to the cluster program. This bug was introduced in June in version pre35 when the attempt to "Fixed problem with infinite loop in clustering for some special netlists." was incorrectly implemented. Version pre35 is considered defective and should not be used for placement. * Fixed crash in router when some pins are incorrectly placed in the design. Now an error message is output. * Fixed a problem in the detail router's route generate code which was causing a crash. The tell tail sign was the router would output an error message denoting that a logic error was detected. Soon afterward, it would crash. This bug existed in all versions after version 2.0.0 pre34. * Now prBoundary is calculated with only the metal layers during a CCT translation. * Updated the compactor code so that core areas may have negative offsets. * Rewrote the class constraint code so the the default block class is 0 and not 1. This is much more easier to understand and allows the user to assign block class 1 to row 1, block class 2 to row 2, etc. making classes more straightforward. In addition, this is how this constraint was originally envisioned. * Added the icnet properties command so we can manipulate net properties in the translator. * Fixed problem with pad editor orientation bitmap. Orientation 5 referenced the wrong bitmap. * Added more support for power supply partitioning. Initial support for single row partitioning is finished. Optimization still needs work. * Added initial support for define statments in Synopsys .lib files. * Now support row pedestals correctly in the global router when adaptive spacing is enabled. * Now icread_verilog takes -module option so we can flatten the verilog in one Tcl command in the case of the top level module is not the last module occuring in the Verilog. In addition, the default flattening now stops when the flattener encounters a model which has a physical representation. Fixed problem with missing trireg keyword which was causing bogus syntax error reporting. * Added the icflatten_verilog apr_stop command so one can control the flattening on an instance basis. * Now -used_models works properly on the icwrite_ic command when hierarchical cells are present. Version 2.0.0 pre35 ======================================================================== * Added EZedit script to implement an interactive itools library manager. * Added icmodel ports Tcl command to output ports of a pin. * Added -Q (quiet) option for prettier startup output for EZedit. * Fixed crash in route_only case (igrouter) due to changes in internal graph structures. * Fixed channel compaction when one routing layer is much wider than any other layer. * Added initial support for itools interactive editor. * Added -popup option to icrouteable_report so popup can warn users when unrouteable nets exist. * Added itoolslm alias for EZedit. Added version cache to libmanager in EZedit. * Added filter options to the icgds enumerate command. Added MERGE ability to the icgds_define LAYER command. * Added the -ignore_bind_errors command the the icread_ckt and icread_ic commands. Added the icexit_on_bind_error command to handle bind errors in general in the translator. * Fixed bug in parallel placement algorithm which was degrading the results. * Update the parallel host creation and manipulation tool ichost so that it understands the icdaemon and uses it to test the parallel setup. * Improved the graphics behavior when in the parallel mode using icdaemon. Previously startup times were extremely slow. * Added support for clock spines. Now the placer runs twice to place clock drivers such that all loads are either in the same row as the driver or in either of the two adjacent rows. * We now turn off port compaction except for the last iteration when speed is set to fast 20 or greater so compaction doesn't dominate run time. * Added support for uniform sparecell placement. * Added the iccost relax_minjog command to the detail router to control minjog design rules. * Fixed typo which prevented reading ANTENNACELL in the LEF translator. * Added the ability to recognize instance placement properties to discover the instance name. Added the icgds property command. * Added support for extracting the prBoundary from CCT input files. * Added GRID_IOS to .ncons file. * Fixed problem with infinite loop in clustering for some special netlists. * Added power/ground mesh generation interface to the detail router. * Added driver centering constraint to the clock spine constraint. * Added ability for the user to supply the log file pathname. In addition, now we create the .itools directory if it doesn't exist so the default log file will work properly. * Improved error handling capability of LEF reader. Now complains when geometry supplied is in error. * Added the icgds_define SUBSTITUTE layerx WITH layery rule so user can modify GDS on the fly and replace the routing layer input to itools. * Now the placer does not spend excessive time in the final stage placement algorithm when fast placement is requested. * Added icrow given_boundary command in the iplacesc program. * Fixed problem with autodetecting placement scripts. * Added pre_equalize_row option to placer for completeness. * Added ability to allow_row_overlap in the global routers for completeness. This is a risky endeavour as the global routers assume that cells in the rows do not overlap and its use is discouraged. * Improved the IO routing appearance by routing each of the nets in a clockwise order starting from the bottom left pad. * Added pad routing optimization Tcl function for detail router. Added this function also to the place pads dialog box. * Fixed problem with pre_equalization of rows in the placer. Now spacer cells are properly added to the design. The global router performed the algorithm properly and this error is only seen if only placement is performed. * Fixed problem with small misalignment of layers in the detail router. * Added icvias grid_if_possible option in detail router. * Fixed problem with writing out SPARECELL constraints. Previously, there were no spaces between the keywords. * Fixed problems with floorplanner not reading the correct parameter file when performing detail routing. * Got rid of annoying warning message in detail router which states the tile is NULL. * Fixed problem with global nets not routing properly. Problem was that not all global pins were being added to the list of target route pins. * Now spine buffer are assigned using linear assignment so that row overflow is minimized. * Added the icspeed command it iplacesc. * Now we revert to left-edge standard cell placement when row pre-equalization constraints are badly specified. This way a good result with respect to wire length is returned. * Improved result when many spacer cells are present. * Added the icnet globalbind command. * Added missing Wire Length Monitor command to igp floorplanner. * Added the -pin_type option to rowstraps GUI. * Fixed problems with icglobal_nets function. Now output is correct whenever implicit global signals are requested. * Fixed problems with initial bin packing algorithm in the igp floorplanner. * Now core size is properly reinitialized when rerunning the floorplanner in igp. Now we calculate a minimum size for the core based on bin packing and we don't allow the automatic size of the core to go below it. * Fixed problem with output_at_density spacing in global router. * Fixed problem with searching EZ for keywords. Previously it complained that ...icsearch.js could not be loaded due to an unterminated string literal. * Now we make sure that all class assignments to clock spines are properly within the range of valid rows. In addition, centering option now works properly. * Now both icinstance core and icinstance corecell work properly. Some Tcl scripts were referencing icinstance corecell which wasn't implemented. * Added POWER_MESH constraint to .ncon constraint file. * Added icgds_label_instances_from_text option so we can extract instances from GDS when instances are labeled. * Added the icplacepads::assign function in itranslate so we can assign pads to sides if needed. Also added the icrow::assign function so we can extract row info from a placement. * Added ability to reference icmesh GUI capability from an idetailer script. * Fixed problems with stacked vias in contour detailer router. Now generated routes do not create massive design rule errors. * Fixed problems with extracting rows in translator when feeds are present. * Added the depth option to the icgds find command for completeness. Added icgds lookup command so we can get gds layer numbers from symbolic name. Also improved gds commands so that you can either use raw GDS units or design units. Added the -obey_cons and -verbose options to icpad findside command. * Added a tolerance option to the sparecell constraint. * Added the CLUSTER constraint for row-based placment. A cluster may be defined by the user by using the CLUSTER constraint in the .con file. See EZ for more details on the constraint syntax. * Began work on adding CLUSTER constraints to igp. * Added CLUSTER_SUBCIRCUIT constraint to .ncons file constraints. * Fixed problems with trying to fix undersized pins on cut layers in the detail router. This operation should only be applied to routing layers. * Fixed problem with false design rule errors when insulators are present in the routing. * Fixed problem with false design rule errors when insulators are present in the routing. * Added CLASS_EXPR, CLASS_MODEL, and ROW_CLASS constraints to .ncons file constraints. * Fixed problems with -setgrid option to idetailer placepads Tcl script. Now properly support padgroups in optimize pad routing command. * Added icroute_statistics namespace in the idetailer program so that we can make a routing report. * Added stdcell placement capability to the igp program. Now the second generation floorplanner can place stdcells as well. Version 2.0.0 pre34 ======================================================================== * New fat wire algorithm which is far more accurate in determining fat wires. * Fixed problem with global nets in the detail router. Previously, non global nets with the same name were being tagged as global. Now we correctly match by the group number. * Improved the neighborhood report file so that it now reports violations in decreasing order. * Added new algorithm to pre equalize the rows when in ECO mode. This is available in placement when ECO is in effect and equalize_rows is enabled in the parameter file. In the global router, this algorithm is enabled thru by either the enaabling of either eco_placement or pre_equalize_rows. In allow_space overlap mode, pre_equalize_rows is turned on by default. When the desired row topology is rectangular, this algorithm will generally achieve better results in the case of eco_placement or when space is allowed between cells in the row. * Fixed problem with buffering nets in "flat" placement mode. Previously, we only buffered nets in hierarchical mode. * Fixed problem with row topology program not outputting all rows. This occurred with some complex row topologies when rows were split with exceptions. * Improved the rigid neighbor algorithm so that it generates better results. * Unified the grid parameter option so the "grid xgrid xoffset ygrid yoffset" is valid as a parameter for all programs. * Now special width gets highest precedence followed by database width and then minimum design width for a layer. This allows one to route all nets on the layer above minimum design rule width in an efficient way. * Added ORIENT_MODEL, ROUTING_WIDTH, and TIMING_FACTOR to .ncons file. * Major rewrite of the path straightening algorithm in the gridless router. This was needed in order to satisfy notch design rules. * Added the -global, -noglobal, and the -index switches to the icinstance nets command. * Improved error checking for double row height cells. * Fixed problems turning off density display in global router. * Added support for inverse keepouts in the detail router. * Added minimum jog design rule checker in the detail router. * More improvements to detail router's path straightening code and added ability to visualize undersized pins. * Added eco_preview capability in the placer for user debugging. * Added the -e switch to the syntax program to enable more comprehensive syntax checking. The switch turns on keepout checking. * Updated the global router to handle stdcell macro obstructions properly. * Rewrote the supply alignment code so that it is not limited to a maximum number of geometries and now the power supply geometries are analyzed more carefully. In addition, a tolerance amount has been added to the parameter file call "alignment_tolerance". * Major rewrite of the detail routing to handle fat wires correctly. * New antenna rule design checking algorithm which is more accurate and very fast. * Improvements to the floorplanners pad placement capabilities. CORE and PADRING options are obeyed if possible. * Now allow both forms for icpad_ring and "icpad core" itranslate commands. Both commands accept both a list of coordinates or 4 separate coordinate arguments. * Updated the error messages in icinstance so they are less cryptic. * Added the ability to output representatives of each row class in the syntax program so debugging is easier. This is available using the "syntax -e -v" command line options. * Fixed problems with generating keepouts when using the icread_cct command in the translator. * Fixed a problem with the placer which prevented it from finding the optimal placement of a simple inverter chain. This problem resided in the orientation optimization code. * Added the ability to draw pedestals and references in the floorplanners. In addition, we added a crude compaction algorithm for use when user has specified the rows. * Rewrote antenna rule checker and antenna rule violation remover. The new algorithm is much more efficient. * Fixed problem in the detail router when reloading "contracted" netlist. Previously, global net indices were not updated after the contraction. * Added the ability to set the random seed from the command line. This feature was added to allow the create of the icexplore command which will run a set of placement and global routing steps and pick the best one. This is useful when you absolutely need the smallest die/block size. * Added the -lumped and -scale options to the icwrite_routing_sdf command. The -lumped command forces the command to calculate the delay as the lumped capacitance multiplied by the driver strength as opposed to the default Elmore delay of the routing. The -scale option allows the user to scale the result. * Fixed problem with channel compactor which prevented it from achieving maximum compaction. * Fixed problems with the iroute compacting algorithm when macro blocks are present. In addition, icregion_info minspace and extra space commands allow control over compaction constraints. Also fixed problem with origin of designs with macros. * Fixed problem of detail router dropping local connections to global signals. * Fixed crash of detail router due to a samenet via calculation bug. * Updated gds label routine so it puts the label in the center of the instance. * Added logging function to iclicensed so that exit reason is logged. Use iclicensed -bl or use the "license log on" from ladmin -a to enable logging. * Fixed vertical pedestals and vertical rows in placement. The overlap function was using the wrong dimension and so spacing was incorrect. * Added the icrow instances command in the translator so we can detect out of order cells. * Added the density_pad_adjust mechanism to the global router. Now there are two options when using this feature: move the pads or shrink the core when the adjusted cells just don't fit the given pad ring. * Added the EXPAND_PADS and ROWS options to the cons_options.tcl file so we can handle expanding the core using the density_pad_adjust feature and allow pre-existing row definitions in the .ncons file. * Added improved fat wire algorithm which speeds routing over previous fat wire algorithms. This is a major improvement over 34u and earlier versions. * Added more error checking to the SDF output routes function. * Fixed problems with icwrite_sdf function when writing lumped capacitance without including layout pin capacitance. Previous some pins were not output. * Fixed a crash in the detail router which occured when fat wires were *NOT* present. * Fixed problems with the design rule checking built into the detail router. Previously, it was misssing some fat wire errors. * New code to handle longer sets of inverter chains properly in P&R. If all inverter chains are placed in a single row, the probability of the placer finding optimal solutions has been significantly increased (100 out 100 runs). Version 2.0.0 pre33 ======================================================================== * Fixed typo which prevented drawing of ports in the translator when viewing in itools design mode. * Added overlap_algorithm parameter to the parameter file. This allows the user to control the overlap algorithm selection. The choices are best_fit and ordered. The ordered algorithm is necessary for the ECO flow. The best_fit algorithm was the original algorithm and it was intended for the gate_array design style. The default algorithm is best_fit for gate_array and ordered for standard cell design styles. The algorithm is only executed when rigidly fixed cells exist in the design. * Added the -append, -nocons, and the -fixed_xxx options to the icwrite_ic and icwrite_con commands. This allows scripts to filter output fixed constraints. * Added IO constraints processing to the icconstraints namespace in the translator. * Fixed a possible infinite loop in the generation of rows. Added support for vertical pedestals. Now we tell user when core-macro-rows option of icgenrows is in a state which would generate an unexpected row topology. Now icgenrows numrows command acts more sanely. * Rewrote compact_ports parameter to the track suffix so the spacing resembles the detail routing syntax which is easier to comprehend. * Improved the switch (options) placement algorithm when unconnected nets are present. * Fixed problem with instantiating griddless routing in the gridded router when a grid overflows with more than 3 nets at a grid. * Fixed problem with the generation of the path geometries in the contour router. Removes some minor notches. * Fixed problem with global router outputting pin groups which overlap. This creates unnecessary congestion. Now we automatically detect wired-or nets. The user has the option to allow or disallow the presence of cycles in these nets. * Fixed problem displaying solid ports and the mst connections in the itranslate design drawing program. * Added the -portwidth and -portheight options to the icportcells command in the translator. This now allows the user to control both the cell and port size of the automatically generated I/O cells. * Added right margins to some messages for prettier output. * Fixed Bugzilla #26 by rewriting directory structure of the floorplanners. In addition, fixed a major problem with the floorplanners. Both floorplanners ignored the output of the global router. Now both read the results of global routing properly. * Added initial support for reading CCT session files. Very rudimentary. * Added support for CORE_TO_PADSPACE and MINPADSPACE to the itranslate ::icconstraints module. * Added the ::icplacepads::reroute command so the user can reroute just the IO pads if desired. * Fixed problems with log files winding up in strange places due to conflicts in the user path. Paths that include "place" in the name were causing the log file to be put in an unexpected place. * Fixed problems with iclayers pitch command which was incorrectly using pattern vias in the simple pitch calculation. * Fixed problems with iclayers pitch command which was incorrectly using pattern vias in the simple pitch calculation. * When in ECO mode don't due H-tree net buffering unless requested. * Added the icmodel routing_partition command so we can mark the routing center for virtual routing and abstract generation. * The icremote_server command has been updated to register the output errmsgs so we can redirect them to the socket. * Fixed problems with updating hot keys when editing commands with more than one word. * Fixed problem with PRIORITY nets in the global routers. They were being processed in the incorrect order. * Fixed problem with unlap algorithm moving cells a long distance when rigidly placed cells are present. * Added ROUTING_PARTITION keyword to the model syntax so we know the routing abstraction partition line. Using this we can generate better abstractions. * Now we detect and warn the user when an icwait loop would be problematic. If no interpreter or remote server is available, we skip over the icwait command. * Fixed problem in global router when a COVER cell had pins far outside the bounding box of all other data. * Major enhancement to the global router to reduce number of tracks when rigidly placed feedthrus exist. If you have any rigidly placed cells in the row-based core, this version will give great advantage. * Added icposition screen command so we can implement the icpointer::warpto command. Added the icpointer namespace so that user can warp pointer to desired positions on screen. * Now support fake H-trees as a way to do balanced routing. Error checking is suppressed when a skew constraint of -1 is supplied. * Added icconstraints::extract_cover_cell_neighborhoods in order to generate neighborhood constraints. Added new icgeometry bloat and merge operations to support this Tcl. We also added a -minsize argument to control the size of the smallest neighborhood. * Fixed problems with icrow density function. * Added the INSULATOR and _ICGENERATE_ keywords to the .lib file syntax so we can support options better. Switches which are normally closed can be modeled as an INSULATOR which allow the router to connect to the proper terminals and still allows LVS to work properly. The _ICGENERATE_ keyword allows ports to be generated as routing in the output file. * Increased the number of possible defined vias between any two routing layers to 16 from 8. * Added icresistance_route_costs which convert resistance properties of vias and metal to costs. This necessitated the addition of the iclayers resistance and icvia resistance commands. * Added substition lists to icwrite_placement, icwrite_gds2, and icwrite_skil_placement functions to allow replacement of models in these routines. * Added the -mcr_include_origin option to the icgds_define BOUNDARY command so the MCR calculation is unambiguous. * Fixed problem with hierarchical placer entering into an infinite loop. This was caused by no clusterable cells in the netlist. Now the syntax program detects this possibility upstream so that the appropriate control is performed. * Restored copy up feature of the .pl1 file to the itoolsdata directory. This was made inoperable when the directory structure was change in pre30. * Now icdaemon commits suicide when the file icdaemon_suicide is present rather than when icdaemon is not present so we don't have trouble when NFS acts up. * Improved the error messages when a layer is out of bounds, that is, when a user supplied layer is invalid. * Added support to handle undersized pins once again in the gridless router. In addition, we now use a more thorough algorithm to check for undersized pins. * Fixed problem with placement annealing schedule when using hierarchical algorithm. Temperature schedule was getting set incorrectly for large designs. Added a feature for advanced uses to control the exact value of the timefactor. If timefactor is specified as a negative number it will be treated as an absolute number and directly modify the timing cost. Otherwise, the user supplied time factor is used as a scaling factor based on accumulated statistics as our paper states many years ago. * Fixed problem with the ladmin -sq command crashing on some machines. This was due to a coding mistake in the RPC code. Unfortunately, this bug is being circulated in the latest tirpc versions on the net. * Fixed problems with idle task update of the graphics when moving and picking cells. Now you can even scroll the screen during a cell move. * Added simple cell alignment tool to the idetailer GUI. * Added icdraw instance_detail so that user can control look of instance separators in the detail router. * Fixed crashes when SKEW constraints are present in the floorplanner's netlist. * Fixed problems with truncation of routes when using abstraction methodology. Now by default all nets are truncated. Previously, global nets were not truncated and this was causing shorts. * Fixed crash in global routers when feed resources are scarce during feed reassignment. * Added FEED_PERCENTAGE, PAD_TO_ROW_SPACING, and ROW_TILE_MAXIMIZE constraint options. * Added Ignore Global Routing check button for convenience to the Visual LVS checker. * Fixed problem with exact pads being moved in the detail router. Added the -override_exact switch so we can move exact pads if we like but the default is to maintain the position given. * Now iplacesc does not stop executing on error messages. It now tries to do as best as it can. * Now we support the ROW option to compact_ports so we can place option cells away from the rows. * Added output file support to itranslate GDS support. Fixed problems with dumping cells with dollar signs in their name (pcells). * Improved the icnet isolated command in the detail router so that all sets of pins are returned when the isolated pin is a set of pins. * Fixed design rule problem with diffnet spacing rules in the detail router. Bug # 20. * Fixed problems with routing going outside of the routing region. Bug #27. * Fixed problems with the icrestore -keepouts command. This command did not process fat wire rules properly. * Fixed problems with added a via placement in the GDS2. We were incorrectly adding an offset to the coordinates of the via placement. * Fixed problem with connecting to the correct position of a freeway during feed assignment in global router. * Now we report naming problems when performing special trunk routing of clock grids. Bug #15. * Fixed problems with placing vertical rows. This problem exists when option cells exist and/or only vertical rows exist. * Added support for RIGID_NEIGHBORHOOD constraints. These constraints require the instance to remain in the neighborhood and every effort is made to achieve the constraint. * Now properly restore net bounding boxes upon a restore in the detailer router. This was preventing some nets from being routed. * Reworked code to mininize fat wire rule design rule errors. More fixes will be applied to version pre34. * Rewrote SDF output code so that user has more output options to control the output. See icwrite_sdf_routes for info. * Fixed problems with output filtering of equivalent nets in the detail router. Previously, it was duplicating the output unnecessarily. * Improved the code for pin connection points when pins are undersized. Version 2.0.0 pre32 ======================================================================== * Fixed problem with notchfilling when using the gridded router (only the gridded router). Initialization problem was creating donuts. * Fixed problem with improperly displaying the program options of iroute. The -d and -do are two different switches and it was confusing to users. * Now we support a prerouting constraint file which contains the exact order of the prerouting pin locations. This is very useful in customizing the pin placement used in prerouting. If an entry is not found for a model, then prerouting reverts to original algorithm. * Fixed a problem with initialization of certain types of obstacles during detail routing. This problem could lead to design rule errors. * Fixed a problem with too many open file descriptors during translation. This was especially bad for CCT translation. Added a user controllable limit to the number of messages when nets cannot be bound. Version 2.0.0 pre31 ======================================================================== * Major rewrite of the detail router redraw code in order to speed up redraw times. Now manual editing of large designs is much less painful. * Fixed major placement problem for very large clock synthesized designs with timing constraints. Due to an off by one problem, the last stage result was being ignored and the initial state was being restored resulting in suboptimal placement. * Now we check to make sure spacing tables and wide wire spacing rules given by the user are consistent in the detail router. First attempt had some problems and now it is rectified. * Improved the EZ gds2 interface so one can read in a gds2 map file. * Improved EZ grand.do script generation. Updated for new tablelist version. * Added the -libname and -no_defs options to icwrite_gds2 for more output control of the GDS2 (itranslate program). In addition, we added the -only_referenced option so that only referenced cells are output into the GDS2. * Added the icboundary stdcell command for handling the core in mixed stdcell macro blocks in the detail router. * Improve redraw times for zoom functions. Now zoom functions respond immediately. * Fixed problems with crash of placer when no nets are given. * Fixed major problem with prerouting cells. Ports that spanned multiple columns were not being handled properly. Now such cells are prerouted correctly. * Added clock grid for paranoid clock tree distribution. This method has extremely low clock skew at the cost of a bit more routing. The placer now outputs the itools.ckt file whenever clock trees are present as it should. * Fixed problem with translator using tremendously large amounts of memory when reading in a routing. * Added core abstraction for final step of routing to ease time and memory requirements. * Added trunk routing support to the gridded router. In addition, the contour router now supports both trunk and trunk only options. * Fixed parsing problem with icread_cct command. It didn't understand rotated vias in the image file. * Fixed problem with contour router outputting a unconnected net. The router did later connect the net but with a minimum area mistake due to the underlying path generation problem. * Added paranoid via processing to make cleaner routing in the contour router when "fat" wire rules are present. * Added abut attribute to begin support of pins which are routed by abutment. * Added support for PEDESTAL constraints in the row definitions so users can define alignment positions. Also updated row_adaption to handle rows aligned by offset properly. * Now report when 0 nets are present in the design. * Fixed overflow problem in the placer when design is immense. * Fixed problems with ripup and reroute in the gridless router. The algorithm was not effective as it should have been because of a typo. * Fixed problem with routeability analysis in that some nets were marked unrouteable even though they were routeable. * Fixed problem with global router not correctly connecting abutting pins properly when macro cells are present. * Fixed crash in visual design rule checker when notchfill rule is violated with an obstacle. * Began work on a verification option in the iroute control program so we can verify routed designs in the detail router. * Fixed crash in icread_cct command when keepouts occur in the structure section. * Fixed problem in the command icgds enumerate routine which was erroneously returning the wrong data. * Updated syntax program to output class offset info into the .stat file so that we can support pedestals properly. * Fixed problem with the icfile_build only option in iroute. Now when it appears in the .rdo file, the input files for the detail router will be built without executing the router itself. * Now feedthrus are drawn orange so we can see DRC violations better. * Fixed problem with virtual keepins which in some cases generates DRC violations in the row routing. * Added the -e switch to iflow so that errors can be display in graphics even if -nographics was issued. * Added more options to the itranslate command "icreorigin" so it is more flexible. * Fixed CCT translation problems with via constraints in image files. * Improved the row exception capability in the floorplanner. In addition, we now properly construct row configurations when given a target number of rows and macros are present. * Fixed problem with wide wire spacing rules when unconnected pins are wide wires. Now we process unconnected pins so that they make wide wire keepouts. * Now when require vias is off in the parameter file, via errors are reported as warnings so that we don't prematurely kill a placement only run. * Improved the visual DRC checker so we can turn of highlight display. * Improved wide wire processing and added the "icrouter fat_wire" command to control the wide wire processing. In addition, we now align vias over pins so that we can avoid creating notches. * Added missing run time stats to the detail routing control program and now always give the runtime stats in the detail router at the end of execution. Version 2.0.0 pre30 ======================================================================== * Fixed problem with variable pad placement when core is offset from zero. Previously, code assumed zero and this is a problem when the core is not zero. * Fixed problems with -multi_cell_row mode at the entire step. The detail router was not adding the proper pins to the database resulting in unconnected routes. * Fixed problem with cutting out geometries with the icgrid punchout command. Now the command no longer processes global signal pins, ie. power/ground ports. * Fixed problems with assigning the synthesized flag when reading in the routing (.rte) file. Now all added spare cells are marked as synthesized if they weren't originally in the netlist. This was necessary to fix a problem when writing out the Skil placement code. Version 2.0.0 pre30 ======================================================================== * Fixed problem with translate omitting required covered cells. * Now the icconstraints module automatically sets the global pin type from the global net definitions. * Model the core cell macro in floorplanning much more accurately when the user knows how many rows of stdcells that they want. * Added the "iccompact_channel -simplify" to save memory during gridded region routing. * Fixed crash in translator when pin attributes were present in prerouting. We added the icpin attributes command which is used in the preroute.tcl module. Also fixed a crash when models are freed. Improved error reporting in the translator. * Fixed problem with the 64 bit version of the license server which was crashing in translating the network address. * Improved ripup and reroute code for both gridded and non gridded routers. Fixed problems with determining virtual grid when row height was uneven. * Fixed problems with multiple global pin definitions mapped to the same global name. Previously, we were only matching the first one found. This caused problems when performing power and ground routing. The detail router was reporting shorts where there wasn't a problem. * Now iroute can use the miscellaneous Tcl library. It is useful to grid the instances. Now iroute can grid the results if a grid is defined using the icgrid command. * Fixed problems with the flow.onlyroute1 flow. Now global router reads a top level .pl1 file if is supplied. This flow was broken by the new directory structure. * Added more messages to the iclicense -dv option. Now the license server tells which license file it is reading. * Added COREAREA and NUMROWS processing to iccons_options module. * Fixed offset problem with extracting prerouting in the translator. * Added the optional _ICSYNTH_ statement to the MODEL syntax so to be consistent with instance data and to allow recognition of itools created models. * Added ROW info to the .rte file so we can translate row position properly when the -multi_cell_rows option is in effect. * Added the -sorted option to icwrite_placement translator command so output will be sorted by row then left to right. * Fixed problem with misalignment of rows in the output of the detail router by now explicitly outputting ROW statements in the .rte file. * Fixed problem with poor placement results for large designs (10k objects or better). This problem was accidently introduced in version 2.0.0 pre 29 when buffer code was modified. * Added new feature in the global router to add spare cells to the design when equalizing row lengths. * Added adaptive row spacing to the global router for completeness. It is recommended to do adaptive row spacing in the placer but this allows flexibility. Version 2.0.0 pre29 ======================================================================== * Added ability to flatten and edit gds text labels. More options will be added over time so one can modify any aspect of the GDS2. In addition, we added the filter and id options to the icgds find command. * Added the icmodel pinattribute command so we can modify pin attributes in the translator. * Fixed problem with install pager directions which was introduced in version 2.0.0 pre27. * Fixed two long standing problems in the second generation global router igrouter. First was error reporting path is outside region. Second was the router could not find its targets. * Fixed crash in detail router due to bug in the ripup and reroute code. This was occuring in a very deep ripup in the gridless router. * Added SPLIT_ROW constraints and the icexcept command to the floorplanners to make row blockages easier to enter. * Now prerouting extraction doesn't add a conflicting fixed constraint but uses the one supplied by the user. * Now the icfix_instance get command returns the proper form. * Fixed crash in global router due to mistake in except process code. * Added parallel remote start daemons so parallel execution does not suffer from startup delays associated with rsh/ssh connections. * Fixed problem with multiple redraws during resizing of window. Now we redraw design only once. * Fixed problem with translating gds2 with extended polygon figures. The memory was not allocated properly. * Now we add vias to the output gds2 as placements rather than flag geometry by default. You can still add it flat if you desire with the -flatten_vias option to icwrite_gds2. In addition, you can also specify that vias are created in the gds2 from the definition in the parameter file by using the -create_vias option. * Rewrote width verification code so it uses less memory and uses a faster algorithm. * Added the -strict option to the icvirtual_keepin command of the detail router. This switch insures that region division is exact and no pin cutouts are performed except for vertical pins inside the region demarcation. * Fixed problems with reading macro spacing rules in LEF. * Fixed problems with sequential timing data failing with scalar setup times in the floorplanner. * Fixed short and wide wire spacing design rules in detail router. Some wide wire errors may still occur in the gridless router and will be fixed in next rev. * Fixed problem with duplicate menu command in igp.tcl. * Fixed ictell_tile function in idetailer. Now it returns the proper tile when draw contours is enabled. * Fixed problem with crash in placer when net exceeds 32K pins. In addition, we added the large_net_threshold option to the parameter file so we can control large net processing. * Added the icgrid instances function to the detail router to in order to insure that regions are gridded. Version 2.0.0 pre28 ======================================================================== * Implemented a new idetailer Tcl command "icnet type" which returns one of {signal power ground special} so we can improve the row strapping command. * Major rewrite of the floorplanners to handle mixed macro/standard cell cases better. Floorplanner global router will expand soft pins into real pins which can be routed. * Fix of a major problem in the second generation floorplanner igp. Cells were jumping out of the core area due to a logic mistake. Now we get much better floorplanning results. * Improved the speed of the contour maze router also known as the gridless router. * Improved the ripup and reroute capability of the detail router by relaxing via constraints. The relative via costs are preserved but the absolute value of the cost is relaxed in order to complete the routing. The new algorithm can be turned off using iccost relax off if desired. * Fixed iroute's compactor so that it properly recognizes the macros of a mixed macro/standard cell design. This program is now also more tolerant of bad density data. * Improved the parallel processing code for the iroute program. * Added the icroute_cleanup Tcl procedure for convenience. * Fixed a problem with the gridded detail router which was causing design rule violation in the top level including the mult_test test case. * Modified the buffer synthesize to fix problems with building H-trees when macro cells are present. Version 2.0.0 pre27 ======================================================================== * Fixed initialization problem with instances which was causing errors in translation related to fixed cells. * Fixed problems with selecting cells for editing in the placer. * Now we put "bad_net" output messages under user control so we can limit them. * Fixed problem with DEFAULT vias with multiple cuts being translated into a PATTERN via. * Now prerouting in DEF file is assumed as FIXED rather than CAN_BE_RIPPED_UP. We added the -routed_as_ripup and -routed_as_fixed switches. In addition, fixed problems with itools language always choosing CAN_BE_RIPPED_UP. * Added the -squareplus option to interpret DEF routing as centerline square plus (GDS2) instead of the default square flush interpretation. Added initial support for ctgen file parsing. * Now detail router tells when it is entering a wait loop. This helps when user has misconfigured the Tcl. * Fixed problems with parallel routing going into an infinite loop. In addition, we fixed a problem with the 1 license for any number of processors. This problem was in the license server so if you want to use parallel routing using only one license, you will need to restart the license server so to use this version and new servers. In addition, we added Expect support to the parallel algorithm so you can even use telnet to log onto remote nodes. This allows total customization of the parallel process. * Now prevent an infinite loop in detail router. * Changed flows and floorplanner programs so that the floorplanners call the simplify program internally in order to complete the versioning ability of all programs. * Fixed problems with icrow spacing command. Now if expansion would intersect the keepins, the keepins are deleted instead of wiping out the instance data. * Fixed problem with EZ search. Previously, EZ search did not work properly with 2 word searchs. In fact, EZ search was not implemented correctly and only one of its four modes was even implemented when Gordon wrote it. Now all four modes are implemented and exact has been renamed to glob-like to be more informative. * Fixed problems with alert boxes in the graphics programs. For example, iplacesc would not respond to reporting its version due to an initialization problem. * Fixed problems with scaling parameters if the RULES section occured in the .lib rather than the .par file. First noticed in igp where core was scaled improperly. * Fixed problem with adaptive row separation algorithm when in gate array mode. * Now the default routing bounding box of a net in the contour detailed router is +-15 track pitches similar to the gridded router. This speeds up routing tremendously. * Fixed problem in the prerouter which prevented the proper completion of the routing. It was due to picking the largest via for a constraint instead of the smallest via. In addition, we added icpreroute_status so the prerouting log file shows the number of unconnected nets and number of design rule errors after prerouting. * Updated warning message for power/ground pin row alignment code. In addition, we now support multiple port geometries properly. * Added support for forbidden placement intervals. * Rewrote over the cell feed thru assignment code so that upper layer feed thrus may be assigned more efficiently. * Improved the scanpath discovery code to issue better warnings and messages when errors occur. * The itranslate icshort code now merges prerouting properly. In addition, it has been updated to handle names surrounded by {}. * Fixed problems with asymmetrical via. Code was rewritten so that it makes better use of routing area and does not create design rule errors. Also improve icrestore -database command when using gridded router. * Now icpickbox updates the coordinates of the second point during rubberbanding. * Fixed problems with poor routing when row gravity is enabled. * Now install program warns about installing 32 bit version of Linux on a 64 bit machine. * Reimplemented rubberbanding graphics to use blitting rather than the archaic XOR method. * Added the iccritical noripup command to the detail router so we can allow the user to keep critically routed nets. * Fixed problem with crash when aligning cells with power/ground rails when standard cells are large and have many power and ground ports. Version 2.0.0 pre26 ======================================================================== * Updated iplace program to use new flow graphics. * Fixed problem in global router which was causing a crash when cell instances were added in the .gdo file. * Added width optimization flow named flow.widthopt1. This flow will iterate until the width of the design matches the target. Width optimization can be controlled with three parameters in the .par file ICSC*width_optimize : ICSC*max_numrows : integer ICSC*width_tolerance : [0 .. 1.0] The first parameter is mandatory if you want to perform width optimization. If width_optimize is missing, then you get the conventional flow. The other two are optional and have defaults of 1000 rows and 10 percent tolerance or 0.1. Of course, you must have the flow set to flow.widthopt1 * Now icpar_option returns the current value of the option when only 3 arguments are given. * Added missing pad options to detail router include contiguous pad option. * Improved variable pad placing algorithm so that wire length is reduced and wires are straighter. In addition, fixed problems with pad permutation algorithm so it now works. * Fixed a crash that occurred in the fast router when routing global signals. * Fixed problem with DEF reader. It had a typo with SPECIALNETS and was missing support for FOLLOWPIN which has now been added. Version 2.0.0 pre25 ======================================================================== * Major rewrite of the iflow program so that it now supports decision objects. By using Expect in the decision object one can now build iterative flows easily. A preliminary flow editor is supplied as well. This program rewrite was necessary to allow width optimization thru iteration. Now it is possible to automatically optimize the width of a row-based design without manually knowing the number of rows necessary apriori. The new program also has a new look. * Now we generate PDF documentation from EZ. The new generation tool is under the Tools menu. * We now include the expect library so we can write expect scripts in itools for more capabilities on starting remote programs. * Now we give better error messages when GDS2 structure name is too long and rename it to XXX#. * Fixed and enhanced ability to handle stipple patterns in the global and detail routing programs. * Added support for DIFFNET spacing rules for via layers. Added the "icrouter via_obs_are_wires" command so that we work around LEF ambiguities. The default setting is off which means via obstacles definitions in LEF are treated as keepouts for any diffnet rule. If you need them to be wires either via_obs_are_wire command or better yet use the VIA_OBS_ARE_WIRES in the design rules which was added just for this purpose. * Added -pin_align option to prerouting so we can position pins in alignment with a specified layer. This is useful when stack vias are possible and the cells are very complicated. * Updated the Commands Help display so that it properly displays all commands in ::icxxx namespaces and now sorts them so you can find commands easier. * Added the LVS visual connectivity checker for helping show unconnected nets. * Added edit cell dialog gui in iroute for convenience. Also updated iroute so that it properly called the Tcl initialization functions. * Added icpad command to idetailer so we can modify the pad placement more completely and easily using pad constraints. We also added pad gui editing items to the EDIT subment. * Modified RELATIVE pad syntax so that both RELATIVE and RELATIVE statements are understood. The second form allows quick conversion from EXACT constraints to RELATIVE constraints by the change of the keyword and is added for convienence. * Changed the default row to tile spacing in the row topology program to 0 from 1 as this makes more sense. The value 1 was arbitrary and causes problems with gridding rows properly. * Implemented a graphics timeout so that slow network connections don't generate the error: ERROR[ICinitGraphics]:Cannot find window for symbolic name:.frame5.frame7.frame1.canvas2 ERROR[initgraphics]:Aborting graphics. Instead we wait for a specified amount of time before generating this error. The default is two minutes but can be set with the itools*timeout option to the .Xdefault file. * Many documentation updates. * Updated the graphics dump command. Version 2.0.0 pre24 ======================================================================== * Fixed problems with LVS problems during entire route. Removed some confusing error messages during gridded routing. * Fixed problem with icrouteable command when using the gridded router. Previously, it was chosen the incorrect routing source so output was in error. * Fixed problem with reading old .rte file formats which did not use the new GROUP keyword. * Fixed problem with global router which was allowing access to both sides even though access was blocked on one side by a keepout. * Now allow core_to_padspace to support the 't' suffix so the user can specify the distance in tracks. Updated EZ so the regions.ddo file can make use of this feature so that pads are not too close during region routing. * Added output message control to the stripes and ring power and ground GUIs in idetailer and EZ. Fixed problems with missing strap dialog in EZ. This was creating a message that the primary layer was not set. * Fixed problem with pad placement when gridding option was set. Now the core is adjusted to the proper size. * Fixed a problem where floorplanner was stuck in graphics wait loop in a non graphics mode causing an infinite loop. Version 2.0.0 pre23 ======================================================================== * Added -ycenter option to the icpreroute command so we can support y-asymmetrical libraries for prerouting. Also now support prerouting with partially assigned pins (pins on the correct vertical layer). * Added gridded router support for the icrestore -instances command. * Added support for multiple grid vias when using the gridded router. * Fixed problem with cells disappearing during redraw when in zoom. * Fixed problems with Postscript printing of design. The upgrade to a newer version of Tcl/Tk was incompatible with previous output method. * Fixed problem with MINAREA rule rounding during translation. Not enough significant decimal places were being output. * Fixed problem with prerouting process output having extra copy of via information. * Fixed problem with igrouter outputting the wrong placement. It was outputting the initial placement and not the adjusted placement. * Improved the printing GUI for printing scaled regions. * Now avoid crashing in the detail router when a pin is described by only non-routing layers. * Fixed major problem in reading parameter files in EZ. The tyacc parser was in error and preventing the correct reading of the paramter file. This resulting in written parameter file devoid of design rules. In addition, we now keep multiple backup copies ala VMS. We also implemented tainting so that we only change the update color to red now when the user actually changes a value. * Improved the EZ startup when specifying a project file. Now the command EZ works with both full and partial pathnames. * EZ now supports reading of the design log file under the Tools Menu. * Improved the power ring gui in the detail router. Now we allow the user to select message mode. * Changed the backup file separator from . to : so file name will be more readily apparent. * Added initial support for minimum enclosed area design rule. * Now we model the world pin of a ICPORTXXXX cell as a logical pin so we don't create a conflict in the physical domain. * Added support for RESERVED_LAYERS which allows the user to avoid using a layer or set of layers in placement and router even though the layers are defined as routing layers. * Fixed problem with missing prerouting when the -multi_cell_rows option is in use. * Fixed gds2 write problem which placed all of the cells on top of one another when using the SunOS5-m64 OS. Version 2.0.0 pre22 ======================================================================== * Fixed crash when SITEDEF data is present in constraint file. * Fixed problem with categorizing the last net (alphabetically) in the design as a bad net. This occured during reading the constraints and was due to the new global routing format parser. * Fixed problems with reading routing into translator for final output. * Fixed problem with fast router so it works with spacing tables. Version 2.0.0 pre21 ======================================================================== * Major rewrite of the data structures in order to save memory in the detail router. We still have one more stage of reduction to come. * Added the icrouter logmode and the -silent option to the reroute and delete net commands to minimize I/O load during routing in graphics mode. * Added cells_may_abut feature so that we can abut macros and not require spacing between them. * Improved ripup and reroute capability in the contour router. * Now we save the best result found in the second generation floorplanner and return it as the final solution. * Fixed problem with backslashed Verilog port names. Began work on fixing memory leaks. This version is for Mondowave. * Now detail router works in parallel mode with just one license. We added license_max_tries option to iroute to facillitate this feature. * Now we support N and P implant layer types. * Fixed problems with GDS2 processing creating off manufacturing grid keepout data when adaptive stairstep is on in itranslate. * Added -max_area flag to prerouting algorithm. Added the -open_fail_ok option to the iccreate_abstractions command in itranslate. * Added the -process_only switch to icread_gds2 so we can read all GDS2 in first and then perform processing. Version 2.0.0 pre20 ======================================================================== * Fixed problem with crash in placement program when double height cells are present and the row spacing is nonzero. Updated the floorplanner so that doubleback rows work properly. Version 2.0.0 pre19 ======================================================================== * Fixed problem with crash in cluster program. This crash occurred when the target number of cells per cluster was calculated to be less than 1. Now the target number of cells per cluster is limited to 1.0 Version 2.0.0 pre18 ======================================================================== * Added the ICGR*pre_equalize_rows function so one can equalize the row lengths in global routing when special constraints are present. Normally, this isn't required. This code replaces a Tcl script. Version 2.0.0 pre17 ======================================================================== * Updated icread_synopsys function to parse wire_load_table_option properly. * Added the -timescale option to the icwrite_routing_sdf command. Updated so that arrayed net names are properly output in icwrite_spice_parasitics and displayed in the common nets dialog box. * Fixed problems with double height core dump when fixed constraints are present. Version 2.0.0 pre16 ======================================================================== * Fixed problems with doubleback row generation. Previously, it was failing with the error: ERROR[readblock]:block height is less than 1 for row:2 at (5 19.850) (201.204 19.850) Must exit. * Fixed ring and stripe FROM CORE and FROM IO equations so that spacing is correct. In addition, updated placepads.tcl so the interface is cleaner and able to support core to pad spacing on a per side basis. Version 2.0.0 pre15 ======================================================================== * Fixed design rule and unconnected net problems in gridded router. The unconnected routes were due to an error in the ripup mechanism. Added a new mechanism which can handle complex via rules. * Fixed spacing problem in region compactor when no routing was present. This was causing channel to collapse to zero even though there was a row spacing constraint. We also update the channel compactor to penalize removing tiny slivers one at a time. * Added the missing rules : icrule add WIDTH and icrule SPACING ... STACKDIST commands to itranslate. Also added icvias add_no_geom in order to create PSEUDO vias. Also added icrules add OVERHANG rule and icrules add MINAREA rules. Added dummy filter to translator to remove all dummy instances for testings sake. * Added better error check in EDIF translation. * Fixed draw layer GUI to be correct y size. * Updated translation of Magic files and now translate technology file. Began work on multilayer (>= 3 layers) vias with the addition of PSUEDO vias which can have any number of layers. Currently, they are only used in translation. Future versions will have true multilayer viass. * The detail router now supports a manufacturing grid of 1 needed for support of Magic designs. * Added the -model_obs option to icread_gds2 and icread_magic for completeness. * Fixed problem with global routers moving cells to different rows during row equalization (feed padding). * Fixed problem reported by Silicide ApS where the global router was allowing a rotation of a cell to an illegal orientation. This was occuring in vertical constraint minimization. * Fixed a problem in the virtual keepin code which was not allowing a via connection in the gridded router. * Preliminary support for Sparc 64 bit architecture (v9). This is compiled -O using gcc 3.4.1. Unfortunately, higher optimization levels are unstable due to gcc bugs. Will migrate to Sun 64 bit compiler in the future. Version 2.0.0 pre14 ======================================================================== * Fixed problem with placement gate array mode where cells were being placed outside the left end of the row when the defined row was less than the sum of the total cell width. Now the code automatically relaxes the row length so all of the cells can fit with 85% utilization *OR* the program exits immediately if the new option gate_array_exit is enabled. * Improved the overlap removal code for double height cells in gate array mode. * Fixed problems with removing row length due to feed thru length estimation when conserve row length is off. * Added a new WEB-based registration method in EZ to augment email registration. Version 2.0.0 pre13 ======================================================================== * Fixed problem with icrule add spacing range command. Needed for row spacing. * Added missing DRC check for samenet and via cut obstacle rules in the gridded router. * Fixed problem with the status command returning nets are unconnected when they are connected. This affected equivalent pins in the gridded router only. * Added pattern row separation feature in ifp so once can make a repeating spacing pattern. * Rewrote the magic via translation code for input/output. * Fixed problem with buffer tree synthesis. In some cases, it was reporting ERROR[TWfixcons_init]:block assigned to instance (block 0) is out of range as specified in the constraint file - (# rows = 275) * Added EZ documentation for minimum row-row spacing and illegal spacings for row separations. In addition, we updated the detail router algorithm so that the code will work more efficiently. * Fixed problem with vectored signals in EDIF translation. Version 2.0.0 pre12 ======================================================================== * Fixed problem with LEF translation with modeling obstructions as wires. Added the -remove_port_obs switch to icread_lef so we can support LEF 5.5 port access rule that a pin is accessible is port is less than minimum width + minimum spacing to the edge of obstruction. Some abstract generators generate LEF with this requirement. Updated EZ documentation. * Added the icrule add SPACING STACK command to support via stacking rules for different nets (not samenets). * Added steiner tree wire lengths to .gpth report file. Version 2.0.0 pre11 ======================================================================== * Now we don't write internal spacer cells out to the itools.ckt file. * Now by default, the translator creates a feedthru with as many vertical layers as possible so we have good routing density. * Fixed problem with icinstance exist function returning a message instead of just a Boolean. Applies to all programs as this is in the common Tcl module. * Fixed problems with dumping spacer cells into the itools.ckt file. They should not be present in the netlist. * Finished rewrite of placement code for double height cells. Now row-based placer reports cost after legalization so that cost output is now the legal cost rather than the lower bound on cost. Previously, it was confusing to user. In addition, we now capture the lower cost solution found and restore it at the end if it is lower cost than the final cost. This is very useful for small designs (under 1000 placeable objects). * Updated SOFTGROUPS to work with double height cells. * Added ignore_non_routing to save memory in detail router. * Rewrote icscan discover command to make scan path work for non flip-flop end points. Will change spec of scanpath in a later revision in order to make data checking easier. * Fixed a bug in the notch filling algorithm which was causing crashes. Version 2.0.0 pre10 ======================================================================== * *BEWARE* this version has a bug in the output section of the detail router which causes a crash. This version is only useful for testing. * Completed and tested the code to implement double height cells when using allow_space mode. Work was begun to handle multiple core regions. Currently multiple core regions only work with row exceptions. * Added LENGTHTHRESHOLD to the detail router. Internally, this was implemented using spacing tables. In the next releases, we will make spacing tables available as user input. * Fixed a problem with stacked vias being all located on top of one another. Version 2.0.0 pre9 ======================================================================== * Fixed a very bad bug in feed_obstacles which was causing crashes in both globals routers. This bug was introduced in 2.0.0 pre 5. * Fixed problem in bgexec command which crashed EZ when the command redirected output files. Sent patch to sourceforge. * Added bendcost_threshold documentation to EZ. Version 2.0.0 pre8 ======================================================================== * Fixed problem in syntax program when cover cell does not have a boundary. * Added the TKPLACMENT="before" option to JS_COND statement in EZ to make HMTL documentation writing easier. * Added the autodetect_script option to iroute so program looks for design.rdo file automatically. Also added to placer (design.pdo), floorplanners (design.fdo) and global routers (design.gdo) * Fixed problems with GDS2 and LEFDEF viewer when filename in form was blank in EZ. * Improved routing HTML in EZ. Hopefully, it will less confusing. * Fixed some problems with sending data to InternetCAD.com in in EZ. Some still remain. This is a bug in the Tcl core. Will fix in the next release. * Fixed ifp so it writes the rules properly for its floorplanner. This was missing code as the second generation floorplanner igp was coded correctly. * Enhanced the first and second generation floorplan compactors so that they relax the core constraints in order to achieve a solution. This prevents an overlapping solution from occuring. * Added the require_via option to the global routers so that vias are not required iff detail routing is not required. * Added ability to generate boundaries from sizer rules in the translator. Added the -nosubstitute option to the icgds_def_rule itranslate command. Added the MCR operation to the sizer to support automatic extraction of boundaries. * Fixed problem with properly extracting the I/O pins from an EDIF netlist. Added check to see if we have a case problem when binding ports of an EDIF netlist. * Added the -merge_layers option to the LEF reader. * Added ez:write_design_rule_commands so we can generate a script to generate the design rules. A good teaching exercise. * Fixed problem with creating a portcell with totally bogus size (nan) when the manufacturing grid wasn't specified. * Added the flow.iplace2 flow which is a second generation placement only flow. * Fixed problems with reporting errors in both first and second generation global routers when the pin is a point. This occurs in the standard cell tutorials. * Added bendcost_threshold option to the placers : igp, ifp, iplacesc, and iplacega. This allows the user to trade off wire length for wire alignment. * Fixed an initialization problem in the second generation floorplanner. This was causing an infinite loop. Version 2.0.0 pre7 ======================================================================== * Fixed problems with clock tree synthesis when synthesizing 5 or more levels of buffers. Version 2.0.0 pre6 ======================================================================== * Fixed DEF translator to properly handle REGION definitions. * The contour (gridless) detail router now supports different spacing and width in x and y direction. This allows poly to be fatter in x than in y. * Fixed a problem in the DEF reader when reading asterisk points for a rectangle. * Added icscanpath command to translator so that it is easy to discover scanpaths in the netlist. * Fixed problems with license server FIREWALL command. Previously, squid proxies were not working properly. Version 2.0.0 pre5 ======================================================================== * Updated both global routers so that obstacles on the feed thru layers are taken into account when assigning feedthrus. * Now buffer tree may have any depth if the state is assigned. If the state is not assigned, the depth is limited to 4. * Fixed problems with Synopsys library support. Quoted strings and the define statement were in error. * Fixed problem with virtual pin assignment in the detail router. This was due to a mistake in the cut line calculation used in region routing. * Added better status message when EZ is waiting for a process to finish. Version 2.0.0 pre1 - pre4 ======================================================================== * Updated support for MacOSX Panther. Jaguar is no longer supported. * Added new icmodel subcommands: pin_exists, gate_area, diffusion_area, pgate_area, and pdiffusion_area to allow programming of antenna constraints. * Added library support for GATE_AREA and DIFFUSION_AREA constructs to support better antenna rule checking. * Added new port alternatives feature. * Fixed gridding problem when no manufacturing grid is present. * Fixed problem in accidentally using cover cell to build obstructions. If you use cover cells, you will get much better results. * Added the dreaded net weighting constraints to the constraint file. At InternetCAD, we really don't like net weight constraints but people were clamoring for them. Beware. See our DAC paper for the reasons. * Fixed problems with overlap removal code when allow_space is enabled. In some instances, cell overlaps were not resolved. * Fixed the second generation global router path straightening code for non OTC routing. Now all routes are in their proper region. Still to do : add minimum perturbation algorithm. * Added -remove_overlapping_keepouts option to the icmodel simplify command so that keepouts over pins can be removed easily. * EZ has been updated to handle power/ground meshes. * EZ now has lock-down feature so that use cannot change page during program execution. Changing the page during execution was destroying the integrity of the design flow. * EZ translation now asks questions about the supplied feedthru cell and the extraction of pad constraints. * Global router can now equalize the row lengths when rigidly place cells exist. * Fixed a problem with symmetrical detail routing which caused vias to disappear. * Now iroute draws the routing by default. Previously, user had to use the GUI to turn it on. * Updated the icinstance set command so that it conforms with the syntax of the constraint file. * Fixed problem with the translator crashing when using adaptive stairstep when reading in GDS2. * Fixed problem with incorrect output of routing into .scon file. Data was missing spaces. * Fixed problem with autoflow program which was not executing programs when the mandatory switch was enabled and more than one program was specified as a stop program. * Preliminary support for double height cells (placement only currently) * Improved support for Magic input files using a Tcl technology file. * Improved behaviour of pad placing code in detail routing when variable pads are requested. * Now the icstripe Tcl code may be issued in the detail router when in nographics mode. Version 1.4.0b250 ======================================================================== * Completely rewrote Steiner tree algorithm for the second generation global router. Now the global router and the detail router use the same A* algorithm so that the global router will predict the behavior of the detail router much more closely (besides being a much better algorithm than was originally coded). Now all routes should be connected and variable die spacing of macro cells insures at least minimum required spacing. Still to do: fix path straightening algorithm for non-OTC case and add minimum perturbation so wire length is optimized during spacing. * Support for first generation global routing scripts enhanced to enable the placement of power/ground strap cells. * Translator now supports LEF MANUFACTURINGGRID keyword properly.