# $RCSfile: WHATSNEW,v $ (TimberWolf Systems,Inc.) # $Date: 2024/02/18 22:32:27 $ # # # # Version 2.4.3 : May 15, 2026 * Fixed problems with initialization of graphics mode as mode should be set to error state if initialization hadn't been invoked. * Added proper quoting of instance properties that have spaces in them. * Added sizer centerline bound mask operation to handle proper sizer of undersized pins. * Added support for marking the run number of a set of placements. This allows the creation of a report after all place and route programs have finished. It also allows regeneration of the report at later time. It also allows easier identification of the matching placement/router options that generated the resulting output data. This involved a complete rewrite of the transistor PDF report. It handles the four cases of runs with detailed routing on and off and parallel execution on and off. * Added escape pin limit control in the detail router so we can adjust the algorithm so it can properly detect a pin escape. This was preventing some routeable nets from routing in the contour router due to a data scaling problem. * Added support for instance based parallel routing algorithms. This support allows parallel exploration of various routing parameters and routing algorithms. * Added detail routing support for parallel graphics operations and rewrote the twcost function so that it is object based. Added new twcost pathlimits Tcl command to interrogate and control path limit constraints. * Rewrote the undersized pin algorithm in the detailed router so that it calls the mask layer sizer. Now the algorithm undersizes pin to a centerline and then regenerates it with the proper size. * Added max_threads control the detailed router parameter file. * Added run_number support to the detail router so we can properly support collated reports. * Added support for special comment blocks appearing in Verilog file which was added by various synthesizers such as Yosys. This is due to AI being added to some synthesizers. * Fixed typo in PDF report termination time. Version 2.4.2 : Apr 15, 2026 * Redesigned the parallel graphics code so that graphics is closed in the master before executing parallel code so that the X11 connection is officially closed and therefore cannot drop connections which kill the children. Each child process will open up its own X11 connection and close it so all processes have a unique X11 display connection. * Modified the place.tcl and trans.tcl file to use this new technique. Version 2.4.1 : Apr 14, 2026 * Now we no longer pass the window to the detail router when in parallel execution mode. This should make the connections to the X11 server more robust and less likely to experience a race condition. * Added missing initialization to the placement test code for single thread test operation. This was causing a failure in the normal single thread placement mode. * Added more time and file system sync to the twcapture window command. Now we loop until the snapshot file comes into existence in order to compensate for sluggish file systems. Snapshot capture is slow and needs a wait state for reliability. In addition, we added a new test to the capture check. Now we check for the existence of a file and then try to open it. Opening and then closing the file for read seems to insure that the file is really there and not in cache. * Added debug statements to the capture window command so we can discover failure points in the future. * Added a loop to wait until the run directory is properly created when in parallel execution mode. This loop tries a file system sync and then a read at most 10 times before giving up. This improves the stability of the system. * Added the missing twmessage flush and twmessage suppress_graphics to the base graphics code. Previously, it was only added to the non-graphics message system. * Added twpid Tcl command to all graphics programs so we can perform file system syncs as needed. Version 2.4.0 : Apr 12, 2026 * Major version update to parallel execution through Tcl scripting. * Added incremental control over debugging for parallel development. * Now we no longer abort the program when the logging system can not write to the file system but instead produce an error message. This change was needed to debug parallel execution properly. * Added the twpid numrunning, waitforall, and watch Tcl functions in order to implement parallel execution of programs from Tcl scripts. * Major rewrite of the TimberWolf graphics code to allow proper X11 handoff to forked parallel threads. * Added -force, -hidden, -release, and -window options to the "twgraphics on" command in the placer for parallel operation. Added the -directory option to the "twplace replace" Tcl command so we can run parallel runs in specific directories so the program can keep the data organized by run. Added the twwait flush, detach, and relog commands for parallel operation. * Added twpid sync calls and catch operations so that file operations are synced properly on NFS. * Added call to reset the interpreter properly before calling the code which aligns the transistor outputs vertically. This was previously causing a crash in the placer. * Added the ability to collate sections and statistics into the html/pdf report generator. This was necessary to allow parallel operation. * Added more information to twpid waitforall and added twpid sync routine to help sync file systems. * Added the "twpid dir_exists" command to the set of functions to make sure a directory exists. This was necessary for parallel execution when NFS file systems are not implemented properly or are unstable. * Added suppress graphics mode for parallel operation. This minimizes unnecessary X11 traffic during parallel operation and makes things more stable and less like for an asynchronous X11 transaction to crash the program. * Added "twplace detail_route" Tcl function the placer for completeness. * Now we make sure that the placer's GUI is evaluated in global scope. This was necessary for parallel operation. * Improved detail router analytical solver by adding complex geometry calculations. * Fixed problems with instance attributes definitions. * Added user defined properties to instances. Now use can associate a (property value) tupple for an individual instance. This was missing from the TimberWolf circuit language specification. * Added the twinstance property commands: add, find, delete, list in order to manipulate instance properties from Tcl. * Added support for Kicad 9.0 which needed instance properties. Insured that properties are properly double-quoted. * Fixed a long standing problem (crash) when a Tcl output message contains a percent and the message code tries to perform a substitution when none should be performed. * Added the Tcl "twmessage flush" and "twmessage suppress_graphics" functions for parallel execution of programs. * Added update idletasks call so graphics queue is flushed during a snapshot. Sometimes X11 server would delay in writing data. * Rewrote the transistor report so that configuration is only reported in the run info. In addition, we renumbered the figures so that placement is the a picture and detail routing is the b picture of the run. This removes the unwieldly name files as the configuration is no longer in the filenames. * Added proper move of file names in the parallel mode. Added call to suppress graphics so that X server is flushed at the proper times so we don't create an improper X11 transaction. Version 2.3.55 : Mar 13, 2026 * Added support for switches in channel only. * Now we add the via name to the window manager title for the detail router's manual routing GUI. * Added support for drawing polygons. * Added Xdefaults setting fix_buggy_apple_server option to work around the buggy Apple X11 Server which fails to redraw internal windows. By turning on this option, the TimberWolf graphics package will initiate internal exposure events so that the window will eventually be draw correctly. Apple really needs to fix this bug. * Fixed a crash in EZ when graphics are not available. * Updated the twcritical Tcl command in the detail router so it now understand and can manipulate net priorities properly. * Now we assign the power and ground nets high priority so thay are routed first. This allows them to get straight connections as desired. * Fixed a problem with the hybrid and other routers using the initialization code of the gridded router. Version 2.3.54 : Mar 1, 2026 * Added warning message to transistor power supply code when layer does not exist. * Updated floorplanner so that the twgenrows commands are properly named. * Fixed an initialization problem with the track data structure. * Added support for automatically taking invalid vias out of service. * Added missing call to update of 3D restrictions when folding and unfolding of transistors. This led to a crash during placement. * Now we avoid adding template layers to the switch planes. This was causing a crash in the detailed router. * Fixed routeability code so that it understands pins that need to be skipped. * Fixed a problem in TimberWolfDR's hybrid router when expanding multiple vias. The caused an error message to appear in the log output. * Fixed a problem in the hybrid router which was due to improperly trying to add lines to the tile database. * Added a warning message to the power supply generation code when a layer is not found. * Added debug generation statistics to the analytical router. * Added support for MacOSX Darwin arm64 architecture. * Now the tools do not discard the purpose of a track during processing. * Implemented stud routing for power supply routing. Stud routing will minimize connections between non-primary pins. * Added the stud routing to the twnet properties Tcl command. * Implemented stud routing in the detailed router. * Now all tools try to use the :drawing purpose if only the layer name is given. For example, if metal is given as the layer and it does not exist in the layer stack, the tool will look for metal:drawing as the desired layer. If this is not found, an error will be issued as it is a true error. * Added support for tixfont X resource database configuration. * Updated the shared port algorithm in the detail router so that the code properly identified the ports that need global routing and those that are shared due to placement. * Updated the trunk routing algorithm to detect when pins are on top of each other. * Added the twtrack snap Tcl function. * Added snap algorithm to the hybrid router. * Updated the die area so that it is correct for transistor placement. Version 2.3.53 : Dec 30, 2025 * Fixed problem with Edit Cell dialog box when models contain Tcl special characters like [ or {. * Fixed a problem with the DEF reader in the translator. It was not reading the port pins boundary correctly. * Fixed a problem with the LEFDEF writer in the translator where the tool did not properly output the PINS with the proper placed attribute. * Updated the detail router prerouter algorithm so the translator generates the proper ports for the detail router now that the data structure has been generalized. * Fixed problems in the global router with creating a feed as the code was not updated for the new port data structure. * Fixed problem with the global router port target layer not being defined properly. * Added missing feedthru color to detail routing graphics. * Now the default routing script calls the analytical router first. * Fixed problems with the route pruning bounding box constraint not being initialized properly. * Update the minjog verification routine in the detailed router to give a better error message. * Fixed a mistake that led to incorrectly flagged minjog DRCs being reported in the detail router. * Now we ignore template layers during hybrid routing. They should only be acknowledged as keepout layers not as source pins. * Added center pin algorithm to the the hybrid detail router to make routing look better and to avoid not errors. * Fixed problems with ripping up nets in the hybrid detail router. * Added area_expansion so we don't expand the hybrid grid more than necessary. * Added center pin control option to the hybrid router. The default will be to center the route on the pin. * Added the ability to draw the hybrid search area. * Improved the behaviour of the hybrid router when increasing its search area. Previously, it did not load the hybrid track data structure properly. In addition, it did not reset the expansion data structure properly. * Now prevent a crash in the hybrid router when no path information is found. * Added developer debug and fixed problems with outputting PCB data. * Rewrote the illegal area data structures of the detail router so that has an easier and higer level of abstraction. * Now the detailed router properly check for via cut violations during ripup and reroute. * Rewrote the net priority data structures so that they can support net group numbers needed for global routed nets. * Now the detail router automatically adds routing priority to nets which have been output aligned in the transistor placer. * Fixed a problem in the detailed router where conflicted global routed nets router were being restored to the database where they should have been ignored. This resulted in unconnected routes. * Fixed the majority of problems with unaligned vias in the contour router. Version 2.3.52 : Dec 17, 2025 * Now the detail router outputs any generated template pins on routing layers into the output routing of RTE file in addition to being listed as PINS. Template pins on other purpose pairs layers (pin guides) will not be output as routing but will exist only in the PINS section of the output. * Updated the algorithm in the detail router that calculats the geometry of the template pin guides. Now the values are interpretted as minimum widths relative to the edge of the active areas. * Added missing POLYGON definition in the PIN section for DEF parser. Version 2.3.51 : Dec 15, 2025 * Now pass I/O pins to the detail router but in the ignored state. Necesary to do proper template configuration in transistor mode. * Fixed logic for turning on neighborhood constraints in power domain optimization. Started work on creating proper areas but not complete. * Added code to measure average row length and height for template generation. * Added twnet groupnets Tcl command to support template generation. * Added -pins_only_on_routing_layer option to the sizer so we can ignore pins that were added on diffusion layers. * Added the twvirtual_pin_assign reassign function to the detailed router so we can process template pins properly. * Added the ability of the detail router to output template pins to the output RTE file. * Fixed problems with discovering boundary keepouts in the detailed router. Now we properly update the row dimensions once the cells have been placed. * Fixed problems where detail router did not ignore SKIP pins. * First version of the detail router that generates templates. It currently works for the simple inverter. All steps have been implemented but now needs to be optimized. * Added missing color silver to color pallete. * Added twnets::save_active_state and twnets::restore_active_state. Update twnets::io_nets to take group nets into account. This was necessary for generating proper pin templates. * Fixed problems with accidently adding trunk attribute to transistor output nets. * Fixed problems with user pins in graphics mode. Previously, User Defined Pins menu did not work properly. * Updated the Tcl code for creating template pins for transistor placement. Version 2.3.50 : Nov 17, 2025 * Added twinstance::create_single_row_cluster for completeness and to create test data. * Added plane control to the floorplanners graphics routines. Version 2.3.49 : Nov 10, 2025 * Added the net TWTRUNK_ROUTE option to the constraint file so that the placer can communicate to the router which nets are to be trunk routed. * Improved the readability of the twnet Tcl command in the detailed router. * Added trunk routing to the analytical router. * Added missing code for support of the TW_NO_ABUT implants constraint. * Now the folded cluster has the correct width when no abut attributes are present. * Added gate shading to debug transistor placement designs easier. * Now we automatically add the trunk route attribute to all nets when in transistor mode. * Got rid of error message in the detailed router when pins are on top of each other when performing trunk routing. This is a special case when diffusion sharing occurs. * Improved the quality of trunk routing. However, there is still room for improvement. * Added ability to force ports and pads to have the virtual attribute. This was necessary to allow I/O information to be passed to the detail router without performing a routing connection to the port. * Added the twtemplate command as a beginning step to creating proper templates for routing. * Added missing checks for virtual pins in the detailed router. Version 2.3.48 : Nov 3, 2025 * Fixed problem with creating a fixed constraint referencing the wrong block. * Fixed crash of the twversion -help Tcl command. * Fixed problems with shifting the foreign offset which resulted in the position of cells shifting. * Made the "hide" keyword context sensitive to overcome mistake in the Kicad language which exists in several earlier versions of their code. Need to build test PCBs using the new version of Kicad. * Now we can draw the rows with the power domain colors for easier debugging. * Improved the row evening code for the power domain optimization. Previously, it did not process the row evening code in some cases. * Got rid of an errorneous error message in the placer during power domain optimization stating that there was a logic mistake. This was incorrectly occurring thousands of times. * In the detailed router, now the prune bounding box data structure respects the values set by the user in scripts rather than resetting it during the first route. This was preventing some nets from being routed. * Now each pin has the shared diffusion attribute rather than being set at the entire net level. This was preventing power and ground nets from properly being routed. * Implemented rail routing which allows more efficient power and ground routing by treating the power and ground rails as a common Kelvin connected point. This could be generalized in the future. * Added missing process parameter message for aligned_vias option in the detailed router. * Added some convenience buttons to the plane control gui. Added "All Planes", "No Planes", and "Primary Plane Only" buttons. * Fixed problems with updating global routing information in the detailed router. Code was accessing the wrong net. This caused nets to disappear. Version 2.3.47 : Oct 12, 2025 * Added power_domain_bias as a placement parameter so that user can weight power domains to form either horizontally or vertically. A positive weight will allow the domains to form as horizontal rows whereas a negative weight will bias the optimization to form vertical columns of domains. A weight of zero will let the tool find the natural tendency of the design. * Fixed problems with row evening designs with complex shaped power domains. * Improved the power domain placement algorithm. * Added the twplace power_domain_bias Tcl command. * Now parameter file accepts both iterate and iterations as a placement parameter. * Added the ability to pass a Tcl script to the placers iteration loop. This was intended to modify the behaviour of the power domain optimization but because power domain optimization is a two step process, it must be done at a higher level which still needs to be implemented. Version 2.3.46 : Oct 6, 2025 * Modified the global .rte (DEF) parser so that the version number can occur anywhere in the first stanza. It just makes it easier to read. * Added missing circle code to low-level code to fix problems with PCB designs. This was needed for hybrid router testing. * Added missing initialization to floorplanner for drawing netlist properly for all cases. * Updated Kicad translation routines so that it works with the new twboundary Tcl command format. * Fixed memory access problem in the hybrid detail router. * Updated detail router to use proper call when aligning macros. * Rewrote the statistic output generator used in the placers so that it is easier to read and understand. * Major rewrite of the power domain row evening code. Now the algorithm is more sophisticated and processes constrained domains. In addition, any switch planes are automatically updated. * In addition, fixed the problems with transferring the row topology to the next step of the placement process. * Now that row evening has been updated, turn the default on for row evening. * Now power_domain_width is only an override in the .par file and is not necessary. If not specified in the .par file, it will be calculated automatically. * Now we test to see if switch plane rows have already been defined. If they have, we don't need to do anything. In power domain optimization mode, the switch planes rows are set properly already. This allows power domain optimization to work properly. Version 2.3.45b : Sep 22, 2025 * Added an orthogonal spacing algorithm to the power domain optimization code in the placer. * Added support for user defined horizontal and vertical spacing on a per domain basis including wildcards using the * mechanism. * Added the power domain alignment name to the row constraint so it is obvious to the user which power domain is referenced. The power domain number is still output but the name makes it easier to debug and understand. * Added the TWSWITCH attribute to a row so the multiple planes are properly understood, that is, their purpose. * Add the -switch and -layer options to the twrow add command so we can manipulate these attributes using Tcl. * Now save 3D constraints when changing placement state (either hierarchy or domain change). Previously, this overconstrained the placement erroneously. * Added the TW_NO_ABUT keyword to disallow transistor implant sharing. * Added better error checking for the instance class constraint. Previously, it ignored the constraint if any error occurred. Now it only ignores the constraint if the constraint itself is in error. * Now the double height row checking code in the placer performs a double height row determination for switch rows. This allows the algorithm to properly check when a row is valid for a double row switch. It checks to make sure that the pitch is correct for adjacent rows. * Now we test if a design is specified for row-based placement and no rows have been specified and transistors are not present. This case is only valid for transistor placement. This was causing a crash. Added better message in the floorplanner when this case happens. * Added twrow power_domain_update and twrow switches_exist commands. * Added only route global routed nets option so we can detail route a set of nets first (highest priority). This was added to route outputs of transistors first. Also added these options to the various Tcl commands. * In the detailed router, added missing call to finding connected wires for cells that had no hierarchy in the original data. This was causing switches to be unrouteable. * Added missing center of the pin track line for gridless hybrid router. * Fixed infinite loop during expansion of via option in the hybrid gridless router. * Added new Tcl code to call check of double rows to set row height attributes and check of the power domain code during row generation. * In addition, added missing -routing option to find_track_layers. This was causing the wrong layer to be optimized during switch optimization. * Added check to make sure track direction is valid and added better error message. * Changed the constraint generation code to output the track layer in human readable form instead of layer id. * Added die truncation to track layer listing to support symbolic names for track geometries. Added the -symbolic option to twtrack list command. * Fixed typo in outputting track layer information. * Now twtracks::create_defaults checks to see if track data is already present. If so, it no longer adds default tracks. Version 2.3.44 : Aug 29, 2025 * Added the -noshift option to avoid adding model shift back into foreign offset. Now the default is to add the foreign offset back. This fixes a problems with the toplevel cover cell shifting making the placement invalid. * Added a version number to the RTE output routing file. This was missing and version is part of the official spec and so this does not need to be a comment. * Implemented ignoring polarity model check in the placer. User now specifies which models to ignore using a list of wildcard patterns. * Fixed problem with double height rows and a single plane 1 row. We temporarily convert the switch to a single row to pass syntax checks and then restore the proper size when the switch planes are created. * Added the "twplace switchrows init" Tcl command so we can alert the placer that it should restore multi row high switches to their proper height. * Added missing -nocheck option to the "twmodel rows" command when translating switches. This was a problem when the switch was two rows high and only one plane 1 row was defined. Version 2.3.43 : Aug 25, 2025 * Refactored track code so that all programs that manipulate tracks use the same data structure. * Now the transistor placer understands track templates properly when they are present. * Added the "twtracks instantiate" command in order to support transistor track templates. * Fixed problem with double outputting the track template constraints. * Added visual routing to the contour router. * Added support to properly update the geometric data of power and ground pins which are generated thru Tcl in the detailed router. * Began work on the detail routing function create_routing_template. Version 2.3.42 : Aug 14, 2025 * Rewrote foreign offset code so that it was consistent and that programs itranslate, iplacesc, and TimberWolfDR are all capable of displaying the foreign offset of cells. * Added the WITHIN phrase to the MAXSPACING command for completeness. * Fixed problem with overlap removal algorithm when split rows occur. It was not detecting that overlap was present in this case. * Fixed problems with displaying row attributes properly in placer. * Added the .foreign file to the placement output for transistors so that the computed foreign offset is returned. * Added a new feature to show row overflow. * Now we delay the enforcement of cell overlap until near the end of the placement algorithm. This gives a more realistic result. * Increased the hierarchical clustering placement algorithm threshold to 500 placeable objects. * Fixed memory problems introduced by rewrite of pin consolidation code in 2.3.41. * Added foreign origin translate to itranslate model viewing. * Updated igp so it maintains original offset so we can translate to KiCAD properly. * Added Draw Reference to the detailed router and the translator in order to help debug foreign offset problems. * Added spaces to the editcell GUI so it is easier to read. * Added twverify::verify_row_overflow so we can show users why area constraints are overconstrained. * Now the placer uses an elapsed timer to stop the chain move overlap removal algorithm rather than just counting iterations. The amount of time may be set by user using the "chain_move_timeout" command in the parameter file. The default is 60 seconds which is very conservative. This prevents the placer to spending time trying to resolve hopeless overconstrained situations. * Now the placer performs a verification step to check if row class constrains have been violated. If so, it add the picture to the PDF output. Version 2.3.41 : Aug 5, 2025 * Added apposition and max spacing design rule constraints to the rules. * Added better indentation for CAPACITANCE information in the .lib file. * Rewrote model pin consolidation code so that it was correct and didn't leave out pins. Previously, this resulted in wrong detailed routing. * Fixed problems with missing initialization of instance row index when recomposing clusters. This was resulting in an error during overlap checking. * Added the "twmodel mustconnect" Tcl command so we can translate from all ports under a single pin to a model where all routing ports have their own pins. This forms the equivalent of Cadence's MUSTCONNECT constraint. * Added the "twpath delete_type" Tcl command so we can properly rerun different variants of transistor constraints. * Added the "twrule maxspacing" Tcl command to the translator. * Made transistor folding reentrant and reversible. This allows the transistor placer to explore many variants of a circuit topology. * Added missing pin skip check while drawing the current state of data while in the placer. Necessary for transistor placement. * Generalized the pin sorting algorithm in the placer. Now even pads can have skipped pins. * Implemented the "twtransistor fold" Tcl command for the placer to manipulate transistor folded configurations. * Added maxspacing and apposition control to the twreport_errors function. Added the -trunk option to the analytical router algorithm. * Implemented maximum spacing rule in the detailed router design rule checker. Version 2.3.40 : July 28, 2025 * Added the -index_only option to Tcl "twrows list" command so we can list the rows of a given plane. * Added better error messages for when tracks overlap. * Fixed a problem with placer crashing when neighborhood locations are invalid. * Added the RECT format to the fixed language constraint so once can specify either rectilinear polygon constraints or rect (area) constraints. * Fixed problems with the clustering program not outputting fixed constraints properly. * Improved the compactor overlap processing code so that it now understands multiple row cells such as switches. * Updated the hierarchical cluster program so that it properly understands two row high switches. * Fixed a crash in the placer that occurred when two row high switches existed in the design. * Rewrote the snap_neighborhoods to row code in the placer so that it creates valid areas. The cut areas previously created invalid slivers. * Added create_switch_double_height function to properly configure the upper planes for double row height switches. * Added the twdraw highlite-row -class command so we can display all the rows with a given row class. * Rewrote the output routines so that the placer will always output at least the first 100 overlap problems if they exist. Previously, the output would remain quiet if many overlap had occurred during the placement process. * Now we properly ignore switches in the polarity checking process. * Fixed problem with missing initialization of tracks during some variants of pocket placement. * Now we only consider active layers when checking for aligned vias in the detailed router. * Added checks to avoid crashes when data is completely wrong in the detailed router. * Now the detailed router properly looks for both directions of any given track or template layer to handle wrong way routing. * Added aligned via code to the hybrid router. * Added Visual Routing Control to the hybrid detailed router. It enables the user to view the expansion of the router in real time so one can understand why things don't route. * Added Highlite Row Class column to the Show Row Classes GUI for better debug. * Added the "twrouter path" Tcl command to the detailed router to control the path style. * Improved the algorithm in the detailed router's verify_aligned_vias DRC checker. * Added special row length processing for two row transistor placement case. Added sorting to align transistors vertically for cases without using hierarchy information. * Major refactor of the clustering code to consolidate and generalize the clustering algorithm using in transistor folding. Now folded transistors can be composed and decomposed into clusters. Now the PCB clustering and transistor clustering algorithms share code. * Now the detailed router understands shared pins and allows the routing to proceed properly. Version 2.3.39 : July 21, 2025 * Fixed problem with double height rows not being initialized to 2 rows high internally. * Added guide aliases to the rules file as guide layers may have names not associated with the proper routing layer. The alias makes this association. Added Tcl command "twlayers guide_layer" so we can add guide aliases thru Tcl. * Added mechanism to flatten model and store it along with the unflatten model in the internal data structures. This was needed for the detail router to properly find the entire pin in a hierarchical layout. * Added the -show_depth option to the twmodel hierarchy Tcl command. * Fixed problem in translator when displaying models and trying to identify the port information. Previously, this would crash to missing initialization. * Added ability to control drawing of individual planes in the placer and detailed router. * Added the ability to draw individual parts of the cell hierarchy in the detailed router similar to the placer. * Improved the behaviour of edit cell in the placer so that one can see the original cell info after it has been chosen. * Added the is_suppressed option to the messaging system. This allows for better messages when rows overlap. * Major rewrite of the tracks data structure to support multiple methods of entry. The current order of entry is track templates within the standard cells, track units, and the raw track definitions. * Added ability to draw the centerline and the expanded form of tracks in the placer and detailed router. * Added track_policy and flatten_models parameter file options to the detailed router. * Fixed a mistaken error message during pocket placement. Previously, it complained about cells not being in a row for cells that are fixed outside a row. * Changed default created instance names and models from _icadded to _twadded. * Updated the Verilog translator so it now checks and verifies if pcmap file entry matches what exists in the given hierarchy in the layout. If it matches, no warning is issued. Previously, warnings were generated even though the input was correct. * Now we allow for track guide aliases in the twtracks::process_guides function. * Now we measure switch row height during translation. * Generalized the calculation of transistor shared and non-shared boundaries. * Added plane constrol GUI control. * Improved the detailed router manual editing dialog box. * Fixed problems with typos in the output options Tcl dialog box in the detailed router. Fixed typo in Verification dialog box. * Now polarity mistakes are not fatal during a hierarchial placement error check function. Previously, this was making placement exit early. Version 2.3.38 : June 30, 2025 * Improved the quality of the overlap checking algorithm so it uses a true 3D algorithm. * Fixed a hang in the placer when switches are present. The internal move data structure was not updated properly if the compactor was called. In the case that it hung, the compactor was called on the switches. * Added the -map_to_primary_layers, -nokeepouts, and -convert_conductors options two twgeometry model command so we can properly manipulate switches in the translator. * Rewrote the overlap tool so that in graphical mode it can traverse all of the errors. * Generalized internal track direction constructs. * Added ability to create track data structures from guide layers. * Added code to the detail router to properly extract the guide layer information. Version 2.3.37 : June 22, 2025 * Restored interactive mode to EZ. * Changes made to make PDF creation much better including making next page links work in the PDF and adding a table of contents. * Added the twversion uname command in order to make the default PDF creation defaults tailor for operating systems. * Documented the TRACKS constraint and its use. * Added a check to the code which calculates the average position of a pin or terminal and so it ignores non-routing layer geometries now. * Added ability to ignore fixed constraints during overlap verification. * Reformatted .pth file so that it is easier to read by adding a space between instance name and pin name. * Now prevent a crash in the placer when overlapping rows are present. * Added shared boundary code to the allow space overlap removal algorithm. Added the ability to ignore overlap when both cells have been fixed by the user. * Now the placers edit cell dialog box shows all of the cells valid orientations.D * Fixed a problem with a crash in the placer when complex move types are present. The occurred when the placer was performing random placement. * Updated the shared boundary drawing code in the placer so that it was consistent with the non-shared drawing code and so that it could be highlighted. * Now limit the number of output message telling the user that there is no more than one cell in a row. * Turned off transistor folding for the time being as the code is making mistakes. * Rewrote the power supply polarity code so that it create a .polarity file enumerating all of the problems that it has encountered. It no longer exists if it has problem but continues to perform placement. * Added option -primary_only which is now the default to twtracks::track_template so that we only process tracks with the primary designation. The previous behaviour can be restored using the -all_layers option. * Added the -primary_only and -all_directions directives to the twtracks::create_defaults Tcl command. The default now is primary only directions. Orthogonal bias will be interpreted as horizontal bias. * Improved the behaviour of the twcapture::window command. Now it catches failure properly and allows multiple tries to capture the screen window. * Added options -fixed and -nofixed option to the overlap tool so we can see which overlaps are due to the user fixing cells improperly. Version 2.3.36 : June 16, 2025 * Updated EZ and iroute for ic2xxx to tw2xxx name change. * Fixed wrong dependency in mixed transistor flow. * Major rewrite of the super row ordering algorithm. It was based on the assumption of the last plane being vertical. Now the algorithm is generalized to handle any plane having any orientation. * Now the overlap removal algorithm in the placer reports the cells that it is having trouble removing all residual overlap. In addition, the chain move algorithm is now limited to 1024 iterations before it gives up. The algorithm also now determines the maximum available space in the beginning so that it can avoid a useless costly exploration that would not solve the overlap problem. Instead, it will skip that step and enter the chain move algorithm. The will save time in extremely constrained cases. The hope is that this does not occur near the end of the run. * Added the common twboundary command in order to calculate track extents properly. * Added the twtrack layers command so we can determine which tracks have already been defined in the missing track layer algorithm. * Added ability to delay the call to check for missing track layers until placement when in transistor mode. * Added the -plane option to the twrow number command which will report the number of rows on a given plane. * Fixed problem with the drawing of pins in the placer as they were always being draw regardless of plane selected. * Reset all path weights to 1.0 in the transistor placer. In the future, these will be varied. * Added new algorithm for determining layer to place the switches. * Fixed problems with incorrectly adjusting vertical rows when trying to set the maximum row desire. * Added support for new PIN IGNORE_X and PIN IGNORE_Y constraints which will help implement order_ios properly. * Added the row_based_transistor option so that tools can recognize and verify that they are in the proper mode. * Fixed problems with power rails when the number of switch planes exceeds 1. * Added missing icroute_cleanup and icnum_unconnected aliases. * Added two new Tcl supports functions: trans_config_report_args and igp_supports_transistors. Version 2.3.35 : June 9, 2025 * Added GUIDE type for layer definitions to support detailed routing guides. * Added the -plus and -flush options to the detail router's output command for maximum flexibility. * Added twparallel probes Tcl function and parameter file support. * Major rewrite of graphics code so that graphics can be turned on and off multiple times without causing problems. This included changes to the Tix library so that it is reentrant. * Added ability to identify parallel cores during logging. * Added code to the unlapping code so that we properly calculate the row offset of hardcells which touch any row. This is not needed for hardcells which don't overlap any row. Previously, this caused a crash in the placer. * Fixed a problem in the placer when complicated area/neighborhood constraints exist. The code was missing a call to reinitialize the fixed constraints after row definitions are modified. Previously, this caused the program to hang because the overlap unlapping algorithm became overconstrained erroneously. Also added initialization so the multiple row definitions are correct. * Added the twmessage hostname command for parallel processing. * Added check to Verilog parser so that it is fatal if user specifies a top level cell and it doesn't exist. This should have been in it from the start. * Major rewrite of the Tcl for itools in order to make things more consistent and to make the Tcl Python translator work flawlessly. * Added the twfix_inst rectilinear_neighborhoods option so that the user can specify neighborhoods as pairs of two points and this will be interpretted as rectangles rather than rectilinear shapes. The default will be to recognize neighborhoods as rectangles. * Fixed an annoying redraw problem in the detailed router when code is optimized. Version 2.3.34 : May 1, 2025 * Fixed typo in the placement Tcl script which causing a premature end of the script which enventually resulted into a crash in the placer. * Added missing code to cell packing algorithm in the placer in order to handle multi tier cells within neighborhoods. This gets rid of the inst_neighbor_is_valid FIXME message. * Now support multi tier instances in an area/neighborhood constraint. Added missing check for placing multi tier cells in the correct row. * Now we merge default track definitions and track template definitions properly. Previously, we were dropping the template definitions. * Added missing twinstance plane restrictions unrestricted Tcl command. * Added the remove_switch_constraints_without_tracks function to prevent a crash when track definitions are completely wrong. * Added limit test of class attributes in the placer in order to prevent a crash. * Fixed problems with switch fixed constraints in determining correct planes. Improved the internal algorithm to find proper row when an exact match is not possible. * Added the Tcl twfixinst plane command needed to change switch model planes. * Added missing Tcl code which properly updates the foreign offset of switches. * Added twtrans::update_fixed_switches Tcl function to update the plane and row number added switch plane rows are added. * Corrected a bug in the placer which occured during copy of the row information when rebuilding rows for area neighborhoods. The extra copy of the row bitset arrays caused a placement crash due to multiple freeing of the same memory address. Version 2.3.33 : Apr 20, 2025 * Added the -nocheck options to twmodel rows command so we can modify the number of rows of a model without having rows present. * Fixed problem with the detail router outputting centerlines to the center of the pin when it wasn't requested. * Added initial support for using global routing to implement vertically connected output transistors. * Added extract_subrows_size to support a better implementation of transistor subrows. * Added support for circle keepouts. Version 2.3.32 : Apr 6, 2025 * Fixed problems with row obstacles not being properly placed when rows are complex. * Changed the overlap algorithm so that spare cells do not overconstrain area constraints. * Added the -allow_multibinds to the twinstance bind Tcl command. * Now we automatically determine if hierarchy is helpful to detect transistor output constraints. * Now make sure to take plane into consideration when searching for matching rows in the placer. * Fixed problem with the area constraint optimization code not taking all block classes into consideration especially when rows are added and deleted. * Added the ability to turn subchip routing on and off. * Started work on adding parallelism to small place and route problems. * Now spares cells are properly confined to plane 1. * Now spare cells processing starts later so there aren't conflicts with block constraints. Version 2.3.31 : Mar 23, 2025 * Now we output how many vertically aligned pairs of transistors that are discovered in trans_align_outputs_vertically function. * Make sure that fixed constraints have valid rows bounds. This was causing a crash in the placer. * Implemented POWERDOMAIN_VERTICAL_SPACING into the .con parser. This still needs to be algorithmically implemented in the placer. * Fixed a problem with fixed initial constraints overriding stronger constraints. * Now removing overlap for cells outside the rows is done on a plane by plane basis. Added the concept of active spacer cells to allow the overlap mode allow_space to work properly in more situtations. * Added caching to the primary layer lookup function to dramatically speed up layer lookup when wildcard rules have been furnished by the user. * Fixed problem with area definitions which fracturing rows into improper pieces. * Added the ability to recompute global pins during graphics so that if user moves cells in the placer, the wires are properly updated. Useful for debug. * Added the update_order_ios function in the placer so that the positions of the terminals are realistic. * Added the twplace gate_array option to the placer so that scripts can turn this option on and off. Version 2.3.30 : Mar 3, 2025 * Fixed crash due to heap algorithm not returning proper size. * Improved placement algorithm to account for the number of moveable objects in the current plane being optimized. * Fixed power domain initialization so that it is called at the start of optimization. Still more work needs to be done. Version 2.3.29 : Mar 3, 2025 * Now we no longer check standard cells that have been fixed as hard macro cells for their polarities as they are fixed. * Fixed problems with standard cells fixed as macro being mapped to a row when they do not touch a row. Now these cells are considered to be in row 0. * Fixed problems in measuring the row heights in vertically placed cells. * Added missing initialization when configuring vertical rows. This was causing a crash in the placer and translators. * Fixed crash in analytical router due to the use of the wrong variable. * Found memory corruption due to uninitialized variable in the new subnet constraint code. * Added the twtracks list unit Tcl command to detect when templates have been instantiated. This was necessary to perform proper scriptiong of switches. * Now added design information into the .rstatus file. Version 2.3.28 : Feb 24, 2025 * Added the icmodel::has_attribute Tcl procedure for quickly determining transistor types. * Rewrote low-level data structures to make the storage of double variables more efficient. * Added support for POWER_DOMAIN_SPACING rules. * Added subnet horizontal and vertical constraints. * Added support for changing the NTRANS and PTRANS attributes. * Added support for adding horizontal and vertical constraints from Tcl. * Fixed problems drawing simple pins in the placer. * Added support for ordering IOs. This is done with horizontal length constraints. * Added trans_output_vertical option to align transistor output devices. * Added to the placer the write_lib function for debug. Added trans_output_vertical Tcl command as well. * Now we initialize nets based on the constraint file NET_DO_NOT_DETAIL_ROUTE property in the detailed router. Version 2.3.27 : Feb 9, 2025 * Added a net filter function so we can eliminate bad_net warnings in the detailed router. * Rewrote the subchip mode code so that it uses classes rather than clusters. * Fixed problems with the restore function of the placer with fixed standard cells as hard macros. In addition, fixed info typo. * Fixed problem with the pocket placer not recognizing that fixed cells should not be counted as being in the wrong block class. * Added design information to the placement PDF reports. * Automatically detect if a layer is not connected by any vias and disable these layers to prevent a crash in the detailed router. Version 2.3.26 : Feb 2, 2025 * Added test for default track width in cases where track template does not exist. This was preventing the transistor placer from working properly. * Fixed crash in the instance compactor of the pocket placer. This happened when a switch was placed outside of the corresponding rows. Now we map the switch to the closest proper row. * Fixed an output problem with clusters in the placer. The placer was using the wrong row as its origin. * Fixed problem with the pocket placer's row overflow algorithm when fixed cells are present in the design. Now we properly account for them. Version 2.3.25 : Jan 26, 2025 * Fixed crash in the pocket placer when vertical rows are created due to switches in the vertical direction. The fix was to reinitialize the move data structures. * Now check row constraints based on the proper plane. Not doing this led to unnecessary compute time. * Now we allow the placer to output detail routing files even if there was a previous error. This was forcing the pocket placer to end early. * Added code to prevent crashes even if the internal bin structure becomes wrong. This allows the pocket placer to complete in the presence of errors. * Added missing initialization to the instance optimal position calculation in the detailed router. Version 2.3.24 : Jan 17, 2025 * Added missing verification test to the detailed router. It was missing a check for wires again pin and net data. Now shorts between pins and wires are reported. * Added the snap_to_row option for the compactor so it can properly handle switches. Version 2.3.23 : Jan 15, 2025 * Added missing code which was preventing the compaction of switches to work properly. Now switches should move automatically whenever there is routing in cells in the lower plane which conflicts with the routing in the switch itself. * Fixed problem in the translation sizer which was wiping out the pin IMPLANT information. Now this information is automatically inherited. * Added missing default to plane 1 when reading placement data. This prevented the cell boundaries from being drawn when there was only one plane. Version 2.3.22 : Jan 13, 2025 * Added the ability to select whether instances are drawing the detailed router based on their plane similar to the placer. * Now we make sure that a track is still a valid dimension after routing area truncation. While the code was working, it was outputting a lot of error messages stating invalid line being added to databases. * Added IMPLANT option to a library cell model pin in order to implement multiple implant cells. * Now make sure that transistors are output with the proper boundary. We do this by not storing the modified boundary as TWBOUNDARY but TWBOUNDARY_ORIG. We did make this option programmable by scripting. * Added missing initialization to the twmodel type Tcl command. * Fixed a memory problem when creating a new layer after a layer order command was issued. This was causing a spurious crash in the translator. * Added twtrans::check_grid so we can try to detect when transistor data is inconsistent with the placement grid. * Improved the read_placement function in the hybrid router so that a placement is imported properly. * Added missing code to grid cells to a given placement grid in the detailed router. This only plays a role if the user manually modifies a placement. * Added initial working support for the hybrid router to properly use the analytical solving algorithm. * Improved the hybrid router dynamic grid algorithm for when a route does not succeed. * Added missing samenet via design rule check to the hybrid router. * Now we add vias to the hybrid centerline path algorithm. Vias were missing from the final output when using the hybrid router. * Fixed a crash due to the sign of the fixed orientation field. It was meant to be 2's complement but a compiler update viewed it as unsigned. Now we explicitly coerce it to be a signed number. * Implemented a compaction algorithm to remove overlap between switch layers and layers that exist within other standard cells. * Implement check of half implant masks in transistor placer. Untested. Still need to implement check in unlap code. Version 2.3.21 : Dec 16, 2024 * Fixed problem with switches being output with their bloated size instead of their original size. We now look to see if an original TWBOUNDARY object was furnished with the switch, if so the proper size is returned. Version 2.3.20 : Dec 16, 2024 * Added the -WIDTH option to the twtrack list Tcl command to allow the proper creation of switch rows. Added the -gate_array and -common_area flags to twrow enumerate in order to facilitate the proper creation of switch rows. * Fixed a crash in the placer when switch rows fail to be created. * Major rewrite of the track code to support track width properly. * Now switch row creation code uses the track width as a mechanism for determining row height. * Added ability to see centerline and full geometry of tracks graphically in the placer. In addition, track obstacles are differentiate for easier debugging. * Added ability to see the full geometry of tracks graphically in the detailed router. * Added more detailed analysis of how group capacity is calculated in the pocket placer. * Now the translation process is terminated if the requested section of the track template file is not found. * Added Draw Tracks CLF menu item to the placer for easier debug of track information. * Major rewrite of the switch row Tcl code so that it can support vertical rows properly as well as following the track width definitions. Version 2.3.19 : Dec 9, 2024 * Fixed problems with tracks not properly staying with their defined areas. * Now allow some tolerance to the neighborhood area constraints to account for slivers. This improves the coverage of areas to row class constraints considerably. * Now we handle multiple switch layers through the use of multiple track planes. Version 2.3.18 : Dec 2, 2024 * Implemented track templates using tracks that are aligned to rows. Added boundary information to the track info. This is a major rewrite of the track processing code. * Prettied the output of fixed constraints. Now all in one line. * Added Yblk_unitdef_boundary and added placeholders for tracks the span the die which is needed for track templates. * Added keywords TWALIGN_TO_ROWS and TWBOUNDARY for support of track templates. * Began work on processing complex neighborhoods by combining neighborhood areas. Unfinished. * Fixed problem with the double copy of fixed constraints. It happened in two places. * Added the -nowires option to the Tcl track list command. This was needed to implement the proper valid rows for switches. * Fixed problems with not looking for possible suffixes for loading a placement file in the detailed router. * Fixed crash in the detail routing due to improperly handling path constraints. * Added a missing call to calculate the pad dimension in the detailed router which is needed to properly build the track templates. * Improved the bin packing algorithm in the placer to use the length slack of an instance with row class constraints rather than the number of row choices. This improves the algorithm when some rows are very short. * Now we process the neighborhood or area constraints by fracturing the rows and eliminating slivers in order to simply the contraints in the placer. * Removed the simple test for rigidly placed neighborhood cells. This algorithm wasn't smart enough. Now use random placement (bin packer) which uses slack to determine if their is enough space for a neighborhood. * Fixed a crash in the pocket placer due to the lack of initialization of the unlap code. * Improved overlap code to allow cells to cross into other member rows of a complex row. * Added hack to make pocket placer with many area constraints complete. This allows overlap to occur. :( Version 2.3.17 : Nov 18, 2024 * Added low level memory mapped destructive read to support proper reading of Skill files. Previously, C-comments were not properly ignored when the -ignore_comments option was supplied on the command line. * Added track purpose, track type, and track width to allow the creation of tracks based on a Cadence track template. * Added Tcl commands to help manipulate the track purpose, type and width parameters. * Major rewrite of the fixed code to allow rectilinear fixed neighborhood constraints. * Now the pocket placer now only works in flat mode. It is too complicated to work in hierarchical mode. * Now the pocket placer obeys the user directive for row overlap justification. * Added new algorithm to take neighborhood constraints and fracture the rows if any neighborhood is just part of a row. It then converts the neighborhood constraint to a row constraint to make it more efficient and to insure that the constraint is obeyed even in the presence of left justify overlap constraints. * Moved the placement of check rigid neighborhood as so it occurs after the transformation of neighborhoods to row constraints. Previously, it was reporting errors where none were present. * Now the default for snap neighborhood is off due to the new row cutting neighborhood to row constraint algorithm. * Added subchip options to allow placement and routing of only a part of the design. * The subchip option has a second option to either include or exclude external nets into the wirelength calculation. Version 2.3.16 : Oct 28, 2024 * Fixed memory problem by expanding the size of class and row values to 2G. Added number of rows classes to the .stat file so we can properly initialize instance classes when large numbers of rows are present. Previously, this was causing a crash in the placer when large numbers of rows were present. * Fixed the problem with the detail router complaining about path constraints not being found. * Added a new method to detect if a placement is frozen based on the number of moves with no change in cost. * Added the subchip option so a designer can place and route just a portion of a design. * Fixed a problem in the placer where ignored pins of a net were still being placed when not in the pocket placement mode. * Fixed a crash in the pocket placer after reading back the detailed routing output. * Updated the breakpoint for hierarchial cluster for the pocket placer to be 1000 placeable objects. * Added the ability to automatically expand the track area in the hybrid router. * Now automatically sense the proper settings for wrongway processing in the hybrid router. Version 2.3.15 : Oct 21, 2024 * Added a new stage in the hierarchical placement algorithm to see if the input data is drastically bad. If so, the user can now see the errors early in the computation. * Added the -E or examine_constraints command line argument to the placer. * Now we properly read in the hierarchy cluster placement after creating switches in hierarchical mode. In addition, we now set the block classes properly on the second plane switches. * Added a mechanism in the placer to discover when solving the overlap would be infeasible. Now we don't spend a crazy amount of time in trying to remove overlap when it is impossible due to bad input data. * Improved the cluster input algorithm in the placer to handle more difficult cases when the design is overconstrained. * Improved the code that checks to see if a neighborhood can be converted to the much simplier row class constraints and now it is reeentrant. The advantage of class constraints are that they are faster and easy to check if the constraints can't be met. * Added the ability to snap neighborhoods to cover the entire row so that row class constraints can be used. This function can be disabled but is on by default. * Added the twplace read_hierarchical_placement in order to create the proper constraints for 3D switches. * Began to add the data structures to the pocket placer which will allow the integration of the analytical solver into the new pocket placement global router. * Rearranged the placement of the row evening algorithm in the pocket placer so that a valid placement will created to allow the global router to work properly. In addition, we now output I/O pads to the global router so that all nets should be able to pass the routeability test. * No longer output the placement before row evening in the pocket placer i algorithm as this most likely is an invalid placement. * Now a segment out of region is only a warning and not an error in the pocket placement global router. * Added better help message to the twmessage Tcl function. Also added the twmessage error_count and twmessage warning_count functions for completeness. * Now we don't exit the placer when we have problems with rigid neighborhoods. Version 2.3.14 : Oct 14, 2024 * Added option to default to simple row processing for super rows, that is rows with multiple breaks. In the future, this option will be automatically detected. This option prevents an extremely over constrained problem during overlap that the overlap removal algorithm can not solve easily. * Added extra check to make sure an instance really has a row constraint. This will prevent possible crashes in the placer. * Added check for ignore gate array spacers in the placer. It was incorrectly outputting an error message. Added a ignore neighborhood constraint option so we can handle over constrained neighborhoods. Now properly check for the power_domain case. Added left justify simple mode which left justifies over all super rows. * Major rewrite of the read cluster algorithm in the placer so that it uses the current row planes to determine where to place the cells rather than trying to cross reference the row index which is problematic. This simplified the code and eliminated the possibility of mistakes. * Now we recompute the number of core cells before random placement because the number can change through Tcl scripts. This makes sure that random placment does the best job possible. Previously, it was saying it couldn't place some cells. * Now we look to see if user has put an exit statement in the placers Tcl script. If exit is found, we know break the script loop and perform cleanup operations. Previously, cleanup operations in the placer were skipped. * Now we always perform autodefine double rows processing in the placer if requested even if we don't find a double height cell in the library. We now do this because we may create one during power domain processing. * Now turn off congestion minimization in the placer if there are no pockets definitions. * Fixed crash in power domain optimization due to missing algorithm. The need for this algorithm was due to change in multiple planes for switches. * Added missing conversion to integer to the transistor placer Tcl script when calculating the number of rows using a width constraint. * Fixed problems with power domain algorithm not copying over the random seed file. Now power domain processing is deterministic. * Increased the number of cells that can be processed in flat mode using power domain optimization to 2000 placeable objects. * Updated the code so the power domain bounding box calculation is correct. Previously, it was not being calculated in certain cases. * Added a draw timeout for the hybrid router for easier debug. * Now turn of aligned via code verification code when aligned vias do not exist. * Added simple design rule check for via keepouts that was missing in the hybrid router. Version 2.3.13 : Oct 7, 2024 * Added limit to number of no valid fixed constraints warnings. Now delete any redundant neighborhood constraints. * Added pocket placer restart functionality to debug code easier. * Added more sophisticated mechanism to catch missing instances from the restart file during pocket placement restart. * Updated the restart file format to include the new plane argument. * Now the placer attempts to convert the neighborhood constraints to the more efficient block constraints automatically. * Now the placer only outputs the used switch rows (planes > 1) because they are mostly empty. * Added a missing check for class constraints in the placer when making 2D move exchanges. * Now the placer outputs the current valid placement during pocket placement. * Added the missing message for pocket placement restart. * Got rid of double counting of neighborhood constraints in the placer. * Added fake vias to remove some of the problems with the global router leaving its region. Version 2.3.12 : Sep 30, 2024 * Fixed the neighborhood report verification code which not properly distinguish complex row configurations. Was outputting errors where there were none. * Wrote the missing code of the unlap algorithm for complex row configurations in the presence of fixed rigid neighborhood constraints for all overlap removal modes. This fixes crashes which were previously hard-coded to occur so it would be known if the code was actualy needed. * Fixed a low-level mistake in the file backup algorithm which failed to find if a backup file existed when a compression suffix was present. * Fixed problem with stroke and added the -kicad_pro option to read differently name Kicad profiles. This allowed us to continue work on the hybrid router. * Renamed the gridless hybrid router command to hybrid to make its use consistent. * Now the pocket placer output a neighborhold_report at each stage of the algorithm using by creating backup files. * Now the pocket placer does not perform detailed routing if routing overflow exists as it will always be unsuccessful. * Fixed problems with restoring best overflow found during the pocket placement algorithm. Improved the stopping criteria for the zero overflow case. Version 2.3.11 : Sep 23, 2024 * Fixed the neighborhood initialization code so that it is aware of the desired plane. This was in the constraint but it was missing in the initialization code. * Reduced the amount of output when placing rigid neighborhood cells. Now placer only outputs messages if they can't be placed. * Fixed an infinite loop in the placer due to low level function using the wrong point in its comparison. * Added support for Kicad version 8 which is used for checking the detailed router. * No longer complain about switches being less than one row high. * Added missing Tcl code to handle switches properly when *NOT* in pocket placer mode. * Now that things are improving, allow the pocket placer to use the hierarchical mode. * Now we give a better error message when checking for overlap in the textual mode. We now show internal overlap when there is a problem with the manufacturing grid. * Fixed problems with outputting the wrong transistor placements for the cascode detection circuits. * Added idaho gate check which was missing in the folded cascode detection algorithm. Version 2.3.10 : Sep 16, 2024 * Added new option to the pocket placer called congest_overflow_rows which tells the placer it may add overflow rows. * Implemented new pocket placer algorithm to handle the case of pocket placement without overflow rows. * Fixed memory access violation in the pocket placer due to row height constraints. * Added the cell overlap tool into the detailed router so we can detect overlap problems and fix them. * Added ability to turn off verbose row labels in the placer so it is easier to debug. * Added routing to the placement report for the pocket placer. * Fixed problem with neighborhood errors when user tries to cluster cells in the pocket placer when using neighborhood constraints. The problem was that neighborhoods need to be updated to account for the switches moving to second placement plane. * Implemented the twfix_instance restore command to fix the neighborhood errors * Added the transistor_placement option to the detailed router so that it can know that it is in transistor placement mode. This will allow it to do the overlap calculations properly. * Turn off global preprocess error messages in the detailed router when the global pins are not active so the user does not get confused. * Found that cascode detection algorithm is flawed when the transistors match in cell boundary height but not in width. Disabled this algorithm for the time being until it is corrected. Version 2.3.9 : Sep 4, 2024 * Improved the pocket placer track layout so that it properly follows designer intent. * Added the twrow::maxclass Tcl procedure as a convenience to calculate the largest allocated class. * Now we only add gate_array spacers to rows which have the correct overlap mode. No spacers go into left justified rows. * Now the graphics window default redraw area include all first plane rows. * Changed the desired length of a row to be related to the pocket utilization factor. * Now we delay the building the track data structure until all of the rows have been defined in the pocket placer. Previously, the tracks were not spanning all of the overflow rows. * Major rewrite of the congestion optimization algorithm. Now the first level partition algorithm is both effective and efficient. This is due to a new gradient function. * Fixed an initialization problem in the detail router which resulted in hierarchical data being in the wrong position. * Now allow oversized via cuts in the detailed router. * Rewrote the detailed router so that it no longer requires flattened cells. Now the detailed router supports hierarchical cells. * Added the ability to set the primary layer for power routing. * Fixed problems with managing the memory size requirements of the block multiheight fields. This optimization fixes a memory access violation in the placer. * Now we list the multiple row height cells found in the placer for easier debugging. * Fixed problems with the calculation of the row group block classes in the pocket placer. Previously, they were extending past their proper group of rows. * Added missing statement to the cascode circuit detection algorithm in the transistor placer which erroneously created bogus cascode circuits especially with respect to implant type. * Fixed the track expansion algorithm in the detail router so that it always using the first routing pitch properly. * Added the -drawnets option to the placer report Tcl procedure so that drawing the nets is optional. Useful for debug to turn off nets. Version 2.3.8 : Aug 7, 2024 * Improved the performance of the pocket placer by making the random placement function reentrant. In addition random placement, now properly ignores spacer cells. * Returned the row overlap mode to the correct values during pocket placement which were accidently changed. * Added the twrow overflow_group command so we know which rows are the overflow ones. * Now the pocket placer automatically adds the proper number of overflow rows. The user should not add any overflow rows at all. * The pocket placer now performs row evening on the main group after routing has been performed. * Implemented the aligned vias design rule check in the detailed router. * Fixed a miscalculation in the row length penalty due to an algorithm that is overly optimistic. This fix allowed the pocket placer to get much better results. * Now calculate the proper annealing controller statistics based on a plane basis. * Added the pocket_utilization option to the pocket placer. * Now the initial placement algorithm takes pocket utilization into account. * Now set the proper double_heights_exist flag when performing a single plane optimization in the placer. The wrong setting was causing major slowdown in execution unnecesarily. * Fixed display bug for rectilinear standard cells. * For the time being force the pocket placer to only use the flat mode. * Added the -equivalent option in the detailed router so the added geometries are treated as being electrically equivalent even though they may not be connected. This was needed for power rails that are connected at a later time. * Updated the twtrans::power_rail detailed routing command so that it treats multiple geometries as electrically equivalent rather than must connects. Version 2.3.7 : July 25, 2024 * Added missing test to the cascode folding detection code to account for I/O connections. Previously reported an unknown case. * Now check to make sure that the instance is valid before trying to access its row. This was causing a crash in the common overlap code which appears in the placer and routers. * Added bounds checking on the fixed orientation values. This was causing the stack to be corrected when bogus orientation values were present. * Fixed a problem in hierarchical placement which caused a crash when the row information was wrong due to a row blockage. * Added a new output mode so we can output the manufacturing grid data properly. The old output mode was preventing the values to be output properly in the .log file. * Fixed problem in the detail routing of not properly outputting recursive clusters of transistors. * Added line to state the number of cascode transistors detected. * Added check to make sure we don't call the gridded router code when performing a restore of the instance pins in the detailed router. * Rewrote the detail router's power_rail function so that it can handle multiple rails properly as a list of lists. Added better and more organized output messages. * Added the aligned via and placement grid checks to the detailed router. * Added missing twgrid placement y gridding functions. * Fixed a crash in the transistor placer when only a single transistor exists in a row. * Added the CENTERLINE_MCR operation so we avoid roundoff error when performing these two operations in series in the translator. This fixes the problem with transistors not being properly gridded. Version 2.3.6 : July 11, 2024 * Now we ignore the second plane when performing congestion analysis during the pocket placer optimizer. * Added the -plane option to the twrow add and twrow enumerate commands in order to make search faster and more exact. * Fixed problem with create_switch_rows building a set of invalid rows. * Now the tools understand having multiple different cut layers between two routing layers. * Fixed problem with a crash occuring during the initial stage of the pocket placer. * Added the twgrid placement command to implement various types of rounding. * Added the -plane option to the twrow list command. Updated the functionality of the twrow update command. Added the -direction option to the twtrack list command. * Added the twplace is_congestion_mode Tcl command so we can know in scripts when we are running congestion analysis. * Added check to the switch code which insures that the rows of the pocket placer will be enabled to the ALLOW_SPACE unlap option. Otherwise, cells will remain in the overflow rows. * Updated the create_switch_rows code to understand split rows and the congestion mode also known as pocket placement. Now switch rows in the congestion mode only occur over standard cells rows. Version 2.3.5 : June 11, 2024 * Added check to make sure we don't accidently delete all of the rows during hierarchical placement. * Now we check rigid neighborhood areas for overconstraints. If overconstrained, we exit gracefully. * Added the -noadd feature to twinstance init command. * Fixed problem with nowraparound creating artifacts due to the second plane. * Now the manual editting via tool is responsive to the layer state in order to make debugging a problem with vias easier. * Fixed problem with the translator not copying over the proper implant type when there are folded transistors. * Fixed problem with incorrectly sharing boundaries when the share code is 0. No sharing should occur when either cell has a code of 0. * Fixed problems with scaling the via display code in the router. * Added better I/O pad checking so that it normally ignores global I/Os and gives a more descriptive output of the problematic IO pads. * Added the twlayer order command as a method to perform reordering when ordering information is available. Add the twlayer spacing samenet Tcl command. * Fixed a typo in the translator pin tracing code which was preventing the trace to complete properly. It was not tracing the second layer of a via properly. * Moved the layer order command to the common Tcl library so all programs can call it on demand. Useful for debugging designs. * Fixed the problem with the copy out of samenet spacing rules in the contraint file. Only the WIDTH rules were properly implemented. In this case, the layer names were incorrect. * Now the transistor placer writes out net constraints for the detailed router which was previously missing from the set of constraints. * Now we always round to the closest number of rows instead of rounding up when determining the number of rows for a cell model. Rounding up causes problems when the number of rows is 1 and other situations when there isn't enough rows. * Implemented cascode transistor detection and extraction for the transistor placer. * Now we can differentiate the trunk direction on a trunk route in the detailed router. The default trunk direction is horizontal. * Added code to detect aligned vias in the detailed router, that is, a via choice for each of the exit directions for the two layers of the via. This minimizes notch problems in the router. * Added the -persistent flag to the twrow enumerate command so that enumeration within a loop is time efficient. This was occuring during generation of the rows of the switch plane. * Improved the efficiency of the row search in the placer due to an inefficiency in the quad tree search algorithm. It was using the wrong method to search resulting in linear time complexity rather than the desired logarithmic time complexity. * Fixed a few problems with the initialization of multi-row cells in hierarchical placement mode. * Fixed a crash in the spare placement code when multiple planes are present. Version 2.3.4 : Apr 15, 2024 * Fixed crash in the placer due to freeing the wrong memory. This occurs during hierarchical placement. * Make sure we don't abort incorrectly in the cluster program due to multiple plane rows. * Now we compute the random row imbalance so that designs with crazy fixed constraints do not upset the placement algorithm. * Now we color the fixed cells yellow so the user can see that they are not moved by the placer and if they set the row edge. * Fixed UNLAP_FORCE_GA_MODE in left justify mode in the placer. Fixed inefficiency in removing overlap in left justify mode when fixed cells are present. * Changes made to that the floorplanner is able to optimize each plane separately when multiple planes are present. * Fixed twtrans::find_switches code which was missing an argument. * Added code to correctly build multirow non-permute clusters. * Rewrote the algorithm in the detail router to determine the placement of power and ground templates. Version 2.2.8 : Apr 14, 2024 * Fixed crash in the placer due to freeing the wrong memory. This occurs during hierarchical placement. * Make sure we don't abort incorrectly in the cluster program due to multiple plane rows. * Now we compute the random row imbalance so that designs with crazy fixed constraints do not upset the placement algorithm. * Now we color the fixed cells yellow so the user can see that they are not moved by the placer and if they set the row edge. * Fixed UNLAP_FORCE_GA_MODE in left justify mode in the placer. Fixed inefficiency in removing overlap in left justify mode when fixed cells are present. Version 2.2.7 : Apr 4, 2024 - patch to version 2.2.6 * Now prevent a crash when we have hierarchical placement due to new .pl1 format that has plane information. Version 2.3.3 : Mon 4, 2024 * Added the twtrans::nowraparound and twtrans::recompute_row_sizes so we can block off routing from wrapping around the rows. * Added track manipulation routines so we can modify the pin layer grid so that it intersects the center of pins automatically in the hybrid router. * Added twtracks create Tcl command so we can add tracks from Tcl with any pitch and offset. * Added the twvia geometry -canvas option so we can make a graphics popup window to draw the via geometries in the detailed router. We can find this under the Create Via tab under the Manual Editing option in TimberWolfDR. Version 2.3.2 : Feb 19, 2024 * Now prevent a crash when spares are present. This is due to a bug introduced by new multi plane code. Version 2.2.6 : Feb 19, 2024 - patch to version 2.2.5 * Now prevent a crash when spares are present. This is due to a bug introduced by new multi plane code. Version 2.3.1 : Feb 18, 2024 * Added the ability to draw the die in the detailed router. * Rewrote the graphics functions in TimberWolfDR so that it is possible to open only detail router for graphics. * Added the net via cost function so we can associate via costs on a net by net basis. * Added twcost vias savecosts and twcost vias restorecosts so that we can explicit save and restore all vias to their user configuration before a net is routed with custom via costs. * Updated Tcl commands so that they can handle either a layer or a purpose pair. The layer will default to layer:drawing. * In the detail router, added the missing option to add different via cost on a net by net basis. * Now folded transistor clusters inherit their implant type. This was previously preventing more sharing of diffusions. * Added the power_rail Tcl routing to the detail router to allow scripting of power rails. * Added draw die command to TimberWolfDR graphics menu. * Added the Analytical Routing command to the TimberWolfDR graphics menu. * Added the twtrack extend -die option so tracks can cover the entire die region and are truncated to this region. * Fixed typo in LAYER_ORDER information message. * Now we remove double quotes automatically so that the layer order file is parsed properly. * Added more error checking into the hybrid detailed router. * Added the -share_power and -share_ground options so we can have constraints improve sharing of power and ground connections. Version 2.3.0 : Feb 4, 2024 * Now the unlap functions handle multiple independent placement planes. * Updated code so we don't get a conflict on purpose pair layer names. This was causing erroneous error messages. * Fixed problems with implementation of the enabling of idaho_gate processing. * Major rewrite of the power domain code to handle multiple row cells. * Added check to disallow multi-row switches. * EZinstall now allows a choice on whether to copy the license file or to create a link to the license file. Default is to create a link. Version 2.2.5 : Jan 12, 2024 * Fixed problems with enabled_shared_gates. Previously, shared gates was always enabled. * Added ability to reorder the layers of a design using an external technology file. Version 2.2.4 : Jan 10, 2024 * Improved the code that guarantees that the tracks cover the core area. * Added JUMPLIMIT, PATHLIMIT, SPINELIMIT, XLIMIT, and YLIMIT design rules to the parameter file and automatically pass them to the detailed router. Version 2.2.3 : Jan 8, 2024 * Rewrote the shared boundary overlap removal code so that it works properly for multiple rows in the transistor placement mode. * Added the -append option to the twinstance class Tcl command for convenience. * Fixed problems with not matching keepouts and keepins on a manual delete in the detailed router. * Now placer and detail routers properly displays PMOS and NMOS cell colors. Version 2.2.2 : Dec 4, 2023 * Added upper and bottom pitch dimensions so we can implement standard cell row topologies. * Added the capability to specify plane constraints to the cluster constraints. This allows support of switches on the second plane. * Added the ability to grid switches in normal standard cell mode. * Fixed crash in the transistor placer due to program trying to split the cluster which is not a valid operation in transistor placement. * Updated the translator Tcl to work with the new port data structures. The translator was not extracting I/O pins properly due to not being updated to the new structure. * Now track definitions internally allow wrong way directions so we can unambiguously define the tracks properly without creating small artifacts. * Now model instances can have their plane constrained. * Added the -twdefault switch to the twcluster positions_from_library command so we can set the default mode from Tcl. Added the TWUPDATE option to process plane restrictions properly. * Added the twinstance power_supply command so we can control whether a instance has inverted power supplies or should be ignored. * Now we report the model instance plane values when listing the instances of a model. * Prevent a crash on exit due to the new common Tcl exit function being called with no arguments in some cases. * Added the command twmodel modifyplacement command for completeness. * Improved the initial random placement algorithm used in the standard cell placer when plane constraints exist. * Now check the net to make sure it has pins before attempting to calculate net length. Had to add this check because new code may delete the pins of a net. Without this test, the placer crashed. * Added the Tcl command "twunlap cleanup" so we can properly add rows dynamically in the placer. Added the Tcl command "twplace anneal_switches" so we can control whether we remove the switches for consideration during placement. This is the old way of doing things. Added the command, twplace is_transistor_mode so we can use the mode in Tcl scripts. * Added the ability to control whether the user wants the old or the new algorithm to place switches. The new algorithm will place the switches in tracks. * Added the icinstance::isa_switch and icmodel::isa_switch Tcl commands for convenient script writing. * Added the icconstraints::update_switch_plane Tcl procedure so we can grid switches in standard cell placement mode. Version 2.2.1 : Oct 23, 2023 * Added the enable_shared_gates option so user can turn off transistor diffusion sharing. * Added enable_idaho_gates so the user can enable or disable the sharing of uneven width transistors. * Added twunlap shared_enabled Tcl command. * Now we create the folded transistors such that the source is on the outside of folded transistors. * Fixed memory problems related to transistor folding found in version 2.1.2. * Now the twexit Tcl command has been added to the placement program for completeness. * Added ability to control the reference position of a transistor placement through the configuration string. Version 2.1.1patch1 : Oct 11, 2023 * Fixed memory initialization problem during hierarchical placement when port layers are 0. * Fixed crash in placement during hierarchical placement due to double height cells not being counted as multiple height cells. * Added run id to all figures in reports. * Added the Tcl commands "twplace early" and "twplace clustered" so we can determine in a script whether we are in hierarchical placement mode. * Added the number of rows for a cluster in the .cluster file so that the placer can correctly import the cells during hierarchical placement. * Now limit the number of rows in a hierarchical cluster to powers of 2. This dramatically improved the result. * Fixed hang in the placer when placing small transistor design. This was due to the inappropriate enabling of feed code. Now this code is properly turned off in transistor mode. Version 2.2.0 : Sep 25, 2023 * Drastically improved the time performance of folded transistors with a hierarchical clustering algorithm. * Fixed error in report generating procedure which caused an error when an unformatted 0 was present. * Now the final translate step can handle cells other than transistors when generating final placement step. * Added ability to draw cell orientation and shared boundaries in the detail router so we can debug problems easier. * Fixed crashes in placer and detail router when drawing shared boundaries at a hierarchical depth greater than zero. * Improved the draw cell orient feature so it changes the position of the F character when drawing only shared boundaries. * Fixed typo in twroute_status Tcl command. Version 2.1.1 : Sep 15, 2023 * Release candidate #1 Version 2.1.0i : Sep 13, 2023 * Implemented a shrink and expand algorithm in the cluster extraction routine so that the clusters are properly formed. * Improved the cluster parsing code so that it uses a perfect hash table. * Fixed major problem with unlap code when some rows are left justified and others are allowed space. * Fixed problems with failing when power signal does not exist. * Improved the output of the placement PDF report so it looks very similar to the transistor placement report. Version 2.1.0h : Aug 28, 2023 * Added ability to extract cluster constraints from library model. * Added twcluster positions_from_library Tcl command. * Added half spacing bloat option to enumerating instance data. * Fixed major problem in detail router that was routing over power and ground nets and causing design rule violations. * Fixed crash when double rows exist due to new data structure. * Now switches are bloated by half spacing and not full spacing rule. * Now we build tracks for routing layers in both directions as Cadence does. We can turn this off using the -primary_only flag. * Fixed problems extracting the proper layer from switch to align them. * Improved the readability of the transistor report file. Now it reports the results sorted by wire length and area. Now the files are output using run number and not seed. * Fixed problem with not extracting all via types during processing of transistors. The problem resulted in the via heads being missing on the transistors with the different via definitions. * Added message control to the placer to limit the messages to the screen when port geometry data is wrong, that is, a SOFTPIN occurs in the input data. * Fixed crash that occurs when incorrect data is applied to the twmodel mcr command. Now the routine, outputs the error and properly continues. Version 2.1.0g : July 25, 2023 * Added missing initialization to twinstance multiheight command. * Fixed problem with infinite loop in placer when multiple planes are present. * Improved the pairwise exchange algorithm in the placer for transistor placement. * Prevent outputting the track list twice in to the .scon file. * Improved the performance of placing a second plane of standard cells. Version 2.1.0f : July 25, 2023 * Added the -active option to twlayer routing command so we can easily process just the active routing layers. * Added the twmodel mcr command so we can calculate row spacing properly. * Added a complete brute force look at the required spacings between transistor * rows. This analysis looks at each of the active layers for each of the * row boundaries. Version 2.1.0e : July 13, 2023 * Now rows may have indidual overlap removal strategies. This was necessary to allow 3D placement flexibility. * Fixed problem with outputting plane restrict constraints that are no longer valid and therefore produce garbled text. * Added the -layer_mcr and -bloat options to the plane enumerate command. * Added the twrow boundary modify Tcl command. * Added rewrite_model_boundaries so we can properly recover the original boundaries given by the user. * Fixed problem in saving old boundaries in that the old boundary retrieval did not use the proper -foreign option. * Added the twinstance add_spacers and the twrow desired Tcl commands to support transistor placement. * Fixed problem with routing covering pins when Kicad option is off. Version 2.1.0d : June 27, 2023 * Finished rewriting the global routers so that they work properly with the new port data structures. * Fixed problem with not being able to ripup a net during channel compaction. * Fixed problem with echo and build filters for the routing filter constraints which really encompasses both fixed and unfixed routing. * Updated code so that the standard cell tutorial in EZ now works properly again. * Fixed problem with simple fixed row-based instances causing overlap. Version 2.1.0c : June 22, 2023 * Fixed long standing problem with message system spewing garbage strings. * Major rewrite of the port code so that the data structures are more organized and therefore less error prone. * Added support for calculating routing bounding box or MCR. * Now allow expansion of the pnr boundary from a script. * Now the configuration string uses capital letters to denote mirroring of the rows. * Fixed problem with graphic snapshots not working in graphics parasitic mode, that is, when one graphics program calls another. This allows proper generation of reports when in non graphics mode or hidden mode. * Improved the readability of the transistor mode placer report. * Removed the incorrect syntax error duing transistor placement. * Added ability to move port geometry to a keepout so the detail router doesn't use it as a port. * Added the -wire option to the twtrans::add_model_keepouts function. * Updated twtrans::extract_shared_boundaries so that is properly handle the new port data structures. * Now see if the infinite loop code really is detecting an error. Now it really is a warning when the number of placeable cells is very small. Version 2.1.0b : May 25, 2023 * Added support for shared boundaries in the row-based transistor placer. * Added support for transistor implant models. * Got rid of unnecessary graphics waits in the transistor mode placer. * Fixed problem with .stat file rewrite mechanism in the transistor placer. * Added the ability to change the layer of secondary ports as well as adding the ability to match a port with a given layer over all ports and pins using Tcl. * Added hidden draw graphics support to all programs with graphical interfaces. * Added support for merging ports to the twsizer algorithm. Fixed problem to via trace code in this algorithm. Now traces the connected pieces of a port when in processing models. * Expanded the twrow plane command to allow user to set plane index. Version 2.1.0a : May 23, 2023 * Added the JS_TCL command to evaluate Tcl and put the answer back in the * output HTML. * Added support for a new transistor placement algorithm. This includes generalized placement as well as the more efficient row-based transistor placement case. * Implemented a new graph-based compactor to aid in the placement of transistor designs. Version 2.0.2patch1 : Apr 12, 2023 * Fixed problem with vertical hierarchical placement as the vertical flag was initialized wrong. * Now we only complain about power supply problems when the design is at the flattened stage. Version 2.0.2 : Feb 22, 2023 * Version 2.0.1 candidate1 becomes release version 2.0.2 Version 2.0.1 candidate1 : Feb 10, 2023 * Ported to ARM64 architectures. * Added completed phase 1 compactor to detailed router and floorplanner. * Fixed problems with placing ports when ignored layers and nomerge layers were present. Added missing calls to get_primary_layer_id so that these layers are ignored and not merged during the port placement optimization. Previously, these layers which should have been ignore were blocking ports from going to the proper placement area. * Added support for ignore_layers and nomerge_layer to all programs. Previously, only the placer and the detailed router support it. Version 2.0.1 epsilon : Jan 10, 2023 * Now process tw row blockages so that rows completely covered by blockages dissappear and thereby increase the efficiency of the placer. * Now we support rectilinear clusters. Version 2.0.1 delta3 : Nov 30, 2022 * Added ability to draw unplaced (ignored) nets yellow to show that these nets are not affecting the placement. * Now ignore spacer cells from the calculation of row polarity. * Fixed problems with Kicad parser which mistakely did not allow forms of (keyword). Version 2.0.1 delta2 : Nov 30, 2022 * Fixed crash when multiple runs of a design are run when switches are present. * Fixed problem with placer complaining about not finding a matching block class. * Now detail router can route properly to PCB circles. Version 2.0.1 delta : Nov 29, 2022 * Fixed problem with translating transistor level boundary model instances. * Added twmodel fixedinsts command so the user can manipulate model instance positions. * Updated KiCAD interface so that TimberWolf can exist in its directory without having to rename files. Version 2.0.1 gamma2 : Nov 21, 2022 * Fixed problem with neighborhood constraints. There was a problem with neighborhood calculation when the neighborhood straddled an empty row. * Fixed neighborhood verification tool in the placer. Previously, it could only verify hardcell instances. * Fixed problem with TWPLANE constraint occuring in the wrong place in the .con file. * Added auto_design_style option to the row-based placer so that you can turn off the automatic detection of low cell count placements. By default, it is enabled. * Added polarity_ground_priority and polarity_power_priority so user can order the model net pins which control the detection of row-based power supply polarity. * Added ability to read the kicad_pro file to get design rules. This is new in Kicad 6.0 and now we can support that version. Version 2.0.1 gamma : Nov 16, 2022 * Fixed crash during placement due to cells mistakingly being characterized by being STARNDARD_HARDCELLS which was the old method of fixing complex multirow standard cells. * Added an automatic mode to the placer which changes the design style from stdcell to gate_array when the design has less cells than rows. If left in the standard cell mode, the design would take a very long time to run as the row constraints are unrealistic. With this change, the program will run at normal speed. * Improved the quality of the overlap removal algorithm in the placer. It no longer generates artifacts where cells are placed to the left of the rows. * Rewrote EZ code to use namespaces so that code would be easier to maintain and improve documentation. Version 2.0.1 beta3 : Oct 22, 2022 2.0.1 beta2 : Oct 19, 2022 2.0.1 beta : Oct 17, 2022 * Only add epsilon to foreign offsets when not divisible by 2 evenly. * Fixed crash in placer due to new code missing initialization. * Fixed memory leak in placer and added code to only modify the lengths of the outside rows of a design when in left justify overlap mode. * Rewrote code to properly handle instance version changes for multiple row cells. * Added the Highlite Instance Row Classes menu option to the placer. * Fixed several problems in the block placer unlap algorithm where due to lack of initialization, placer would go into an infinite looop. * Implemented cluster MATCH_ORIENTS constraint in the placer. * Added the TWSWITCH model attribute so we can process models with options properly. * Fixed crash of cluster program due to improper sort of super rows. * Implemented algorithm to remove ports by transitive closure at the start of the placement algorithm and restore them after all other instances have been placed. * Fixed the row polarity error messages when user fixes cell as a standard cell hardcell. Now this is only a warning. Also now the orientation correction code changes the internal state so the graphics is updated properly. Version 2.0.1 alpha : Sept 19, 2022 * Consolidated all of the cluster code so that all programs support the new cluster constraints of initial placement. * Added ablity to optimize clone families of clusters using multiple rows. * Added icmodel::transistor_update_boundary so we can place transistors based on diffusion layers rather than the MCR. * Added the CENTERLINE sizer command so we can extract transistor model boundaries efficiently. * Added infrastructure to handle -width and -numrows to the transistor configuration command. * Fixed problems with drawing power domains properly. It was a clash with the new twdraw power comand. * Fixed crash due to fixing a memory leak in the previous version improperly when performing power domain optimization. * Added the power_domain_update option to TimberWolfSC so one can visualize the power domain optimization. * Added option to turn on and off power domain row evening. The default is now off. Version 2.0.1 z : August 16, 2022 * Added missing center fixed constraint in order to complete constraints for placement. The center fixed constraint has its origin at the center of the placement region. * Fixed problem with twgraphics command returning "1 draw" instead of just a binary flag. * Now we properly calculate the area of the core area when floorplanning multiple planes. Previously, the area calculation was not plane aware. * Now we make sure to update the fixed point constraints properly during reconfiguration in the floorplanner. This was accidently removed in the previous version. * Fixed a problem with the orientation optimization algorithm in the floorplanner. An improper global calculation was creating improper overlap. * Now give an error message and prevent a crash when calling "twpath add" without calling "twpath init" Tcl function * Added the "Placement Report" GUI in the placer. * Fixed several problem with the overlap removal algorithm. We fixed the delete when multiple high row tiles exist. Also, fixed a couple of memory leaks and an initialization problem which caused overlap problems. * Added statistics to the floorplanning and placer report generators. * Began work on multiple row clusters now that the placer supports multi row cells. In this version, the NOPERMUTE option has been implemented. * Added the auto_define_double_rows feature to add double rows automatically to the rows that not mirrored. Version 2.0.1 y : June 27, 2022 * Added a new drawing mode called hidden which draws data to a pixmap so that it can be converted to a .png file. * Added the CLONEFAMILY option to the cluster constraint. * Updated copyright dates. * Fixed problem with cells not being placed properly when in strict * remove overlap mode. This was due to an algorithmic shortcoming in * the unlap_find_best_row function. * Added the ablity to grid the transistors using a linear assignment algorithm. * Added the transistor_mode option to the igp floorplanner parameter file. * Added missing routine name to the twfloorplan command in the igp program. This was causing a crash when any error message was issued. Version 2.0.1 x : June 13, 2022 * Added the twallnets option to the twnet weight command for convenience. It applies the weights to all nets. * Fixed a problem with verifying instance overlaps. Fixed problems with the overlap algorithm when fixed cells are present in the design. * Fixed problem writing verilog files when netlist contain a constant 1 or 0. * Fixed problems with the placer creating overlap with rectlinear shaped multirow cells. * Updated the placer so that long row processing is correctly detected for rectlinear cells. * Fixed problem with subnet constraint when there are exactly two pins in the net. * Fixed problem with the floorplanner not correctly calculating the wirelength for designs with PMOS and NMOS models. * Added the twcore minwidth and minheight commands to the floorplanner. Added missing call to the twpath initialization function. * Added user Tcl callback function to the floorplanner so user can update ignored net pins. * Added an orientation optimization step at the end of the floorplanning algorithm. * Improved the width calculation of the floorplanner transistor placer. * Added the placer option check_power_supply_pins so that the default check can be turned off for designs that do not have power supply pins supplied. Otherwise, this test makes sure that each standard cell has properly designed power and ground pins so the polarity of the row's power supply can be determined correctly. * Added the twinstance iclass Tcl command so we can query the cells internal class from the GUI. * Now properly account row area for a rectilinear shaped multiple row cells. With proper accounting, the placement results are significantly better. * Added row expansion for left justified row designs where even the row packing problem is difficult. This yields much better placements. * Added the twrow reset_orthog command to recompute the orthogonal positions of row-based cells. * Updated the graphics dump routine to allow GIF, PPM, and PNG file formats. Previously, it was hard-coded to GIF. Versio 2.1 w : June 9, 2022 * Added itranslate log_append support capability. * Fixed the problem with icnets::pin_size when there are must connects. Previously, it was only looking at the first pin of the multiple pin set of pins. * We now set the default vertical block orientation to 5. In version 2.0.1u it was set to 7 but it really should be rotated around the y-axis to the coordinate system is increasing in y and not decreasing. This corresponds to the Cadence orientation scheme MXR90 which was previously call MX90. * Fixed problems with neighborhood definitions in the floorplanners. The top side was using the wrong reference. * Added better messages for initial bin packing (aka random_placement) in the gate array placer. Improved the bin packing algorithm so that it finds a better initial solution. The bin packing algorithm now tells the user when the number of placement sites is insufficient. * Improved neighborhood processing code in igp. * Updated EZ code to now append to the log file when call itranslate using the new -l command line option. * Added twdetail::calc_best_via_layer so we can properly relax vias during ripup and reroute. * Fixed problem in the gate array placer which was erroneously trying to do long row processing which only makes sense in standard cell mode. * Now allow the TWPLANES constraint to precede the row information so that we can properly define planes for all all cases. * Added the ability to change cell colors in the floorplanner. This will be extended to all tools in the future. * Updated the compactor to properly report 3D violations. Improved the error messages to report more meaningful information such as the cell index rather than the internal compactor data structure. * Fixed problem with crash when running only single height rows. This was a bug in the placer trying to free multiple height data structures which are non-existent. * Fixed a crash in the placer when we discover double height cells during measuring and no model was marked as double height previously. In addition, we added a better error message and now insure that we only measure core cells. * Added the bin packing and replace design modes to the placement program. * Found and fixed a problem with the incorrect calculation of row lengths in the placer. * Reorganized the monitor TCL code so that it uses a namespace and added search capability to the read log function. * Added the twinstance layers Tcl command so we can retrieve the pin layers found in a given instance quickly. * Now turn off internal redraw mechanism when in pure Tk mode. Version 2.0.1 v : May 27, 2022 * Improved the message control system so the routine names are present. * Added more information to the graphics row label in TimberWolfSC and the translator. * Now we remove the row blockages by shrinking the rows appropriately during hierarchical placement in order to save time. * Now we make sure that row blockages are defined properly by using a threshold in the proper orthogonal direction of row. This was causing rows not to be used when there really wasn't a constraint. * Added better messages so we know which files are being restored in the placer. * Fixed placer's initial bin packing algorithm to use the correct height version. * Improved the row polarity code in the placer so that it doesn't include TimberWolf created spacer cells. * Improved the placer's bin packing algorithm when multiple row cells are present. Version 2.0.1 u : May 16, 2022 * Added a row polarity checker that runs after placement. Fixed a problem with row polarity which occured during placement. * The default vertical block orientation is now 7 and not 4. Orientation 7 is the correct -90 rotation from horizontal rows. * Added missing NMOS and PMOS types to floorplanner during initial bin packing algorithm. * Reduced the time complexity of the pocket placer by running it a minimal amount of time. Useful until the proper code is addressed as there is a complexity bug in it. * Fixed problem which caused an infinite loop during vertical row placement. Version 2.0.1 t : May 2, 2022 * Added support for inverted power supply polarity standard cells. * Added the twmodel instmatch Tcl command for convenience. This function returns the instances matching the model name. * Now properly pass net options to all variants of twwrite_ckt in the translator. * Now add the tieoff signals to the design if they are specified on the verilog command line as tieoff cells. Without the signal addition, erroneous error messages would appear. * Major rewrite of the translator Verilog output code. Now we keep the internal canonical form as long as possible so we properly match the same nets and vectors. * Added the -pintype output option to twmodel nets Tcl command. * Added the start and end index to the twmodel addiopin command. * Added support for handling folded transistors in Verilog. Translator automatically updates the Verilog to use the fingered transistor definitions. * Added the -type filter for the twinstance get command so we can filter instances by model type. This command is useful in quickly finding PMOS and NMOS transistor instances. * Now we color the NMOS and PMOS models in the floorplanner red and orange respectively * Modified the floorplanner so that it doesn't save the wrong initial aspect ratio if the user decides to change the shape. * Allow the user to set the x and y heights of the core to their desired values. * Rewrote the clustering row merging code so that it is general and can handle more cases. * Now the placer does not require flat mode when running large congestion designs. Version 2.0.1 s : March 7, 2022 * Fixed crash in translator when trying to bind model pins. * Fixed crash in iroute due to new overlap code. * Added suport for global layer length limits during placement and routing. * Added CLOSEST_GROUP constraint which only penalizes placement if the closest connection is not connected to same row group. * Fixed problem with failing to open logfile in the translator if the Tcl script fails for any reason other than Verilog read failures. The general script handler was missing a call to the graphics initialization routines. In addition, fixed problem with the name of the log path being to long to process. Now all valid file paths are accepted. * Fixed problem with the twflow program not exiting when the Tcl channel is closed when requested to do so. * Added support for the icconstraints::write_constraints -nocopy and -clearafter functions so this function can be called multiple times. * Added routeablity analysis to the congestion global router in the placer so we can be sure we have a reasonable design. * Fixed a problem with generating the routing graph regions which was creating slivers of keepout regions preventing the proper routing of the congestion router. Version 2.0.1 r : Jan 31, 2022 * Fixed crashes in placer when hardcells are present in standard cell design. The proper code was missing in the new overlap removal code. * Added the verification menu in the floorplanner and placer so that we can verify neighborhood and block class constraints. * Fixed problem with instance constraints disappearing during\ a decompose/recompose cluster cycle. Version 2.0.1 q : Jan 18, 2022 * Added the AREA obstacle to to rectilinear obstacles such as KEEPOUT and WIRES so to make pocket placement definitions easier for the user. This constraint works as a required routing region. * Added the infrastructure to support the SUBNET constraint. While the optimization algorithm is missing in this version, it will allow the testing of user interfaces. * Added the twinstance multiheight and twinstance snap_to_rows to implement the snap to row function which snaps row-based cells to their appropriate rows. * Added the twmodel rows -recalc option so that one can determine the number of rows of a multi row or tier cell. * Now write out 3D plane constraints if given. Fixed the display of 3D cells in translator. * Added use_rows_for_core_area option in the floorplanner so that core area can be inferred from the rows and not the cell prboundary. * Added ability to save off module assigment statements in the translator without the need for flattening. * Added twinstance::snap_core_to_rows and its helper functions twinstance::convert_macros_to_stdcells and twrow::snap_to_rows to allow snapping to the rows when in the floorplanner. * Added display of number of rows to edit cell GUI. * Added -nameonly option to twmodel instances Tcl command. Added the twmodel rectilinear Tcl command so that scripts can recognize rectilinear models. * Added recalculation of row height when reading in a design in the translator so that unlap removal will work properly. * Now make sure that the IO pin data structure is updated when adding additional IO pins to a model. * Added the -copy_model_assigns_to_tw option so that Verilog assignment stays with the model when the design is not flattened. * Fixed a problem with properly adding Verilog model nets when additional nets are added from a script. * Added the ability to set the default block alignment in the parameter file. * Major rewrite of the random placement code to pack multi-height rectilinear cells properly. * Rewrote placer algorithm to more fully support multi-tier cells. * Added Tcl procedure to check the model pin types and convert them to the GND type if needed. * Added support for the SUBNET constraint which constrains a subset of pins of a net. * Added support for the CLOSEST_PIN constraint which constrains a pin to be close to a subset of the pins of a net. * Added the twinstance extract_relative command so we can easily extract the relative positions of macros. * Fixed a mistake in the Verilog writing code which was preventing wires to be added properly. Version 2.0.1 p : August 2, 2021 ======================================================================== * Added a check to make sure the user has made obstacles or pockets over the die area when pocket placement is requested. This was implemented using the new twtracks check_obstacles command. * Added the -type option to the twtracks list command. * Generalized the twnet rowgrouproutes command so that it can work in multiple programs. * Now the translator in graphics mode is layer state aware when drawing obstacles. * Now the detail router automatically corrects improperly defined via cut layers. These are layers that should be cuts but have been defined as some other non-metal layer. * Added the twtracks command and the twdraw tracktype command in the placer to debug track creation. * Improved the track type identification algoritm in the placer so that the placer, global router, and detail router all see the same track definitions. * Added ability to either append or backup log files. * Now output an error message when user tries to alias a primary drawing purpose layer to a non-primary purpose layer as this is the inverse of the proper assignment. Version 2.0.1 0 : August 2, 2021 ======================================================================== * Updated to Tcl Library version 1.20. * Now we update the translator internal settings when setting the max number of block classes. The translator was throwing incorrect errors. * Now global pins connected to a non-routing layer are output as warnings and not errors. * Fixed crash due to missing wrapper around track type. * Improved the detail router so that it now routes mixed segment gridded designs. * Added missing icon fonts.xpm to icons directory. Version 2.0.1 n : July 26, 2021 ======================================================================== * Added capacity constrained option to monitor how close the design is to being routed. Right now net order dependent. Next rev will call optimization to make it more realistic. * Added most of the costs to the global router which control path, length and via jumper limit constraints. Untested. * Added the twroute exec command which calls the detailed router on current design state. Added twcost command to control global routing cost. * Added help option to the setenv.csh and setenv.sh files as well as the ablity to change and restore the directory to its original position. * Added support for translation of Tcl namespace commands in Python and added pure Python mode in twpython to surpress any automatic translation, that is, all Tcl expressions must be explicitly called from Python. * Improved error check in track creation code. Improved the track expansion and flattening code to include unit definitions. * Updated the EZinstall messages to reflect the new setenv.xxx initialization files. * Added ability to draw tracks in the detailed router. * Added the TRACK PASS type which was missing from the list of types of track objects. * The placer now creates the proper track definitions for obstacle and row group definitions. * Tracks definitions no longer a track to touch a row when in pocket placement mode. * Implemented the track router within the detail touer. * Fixed crash in placer due to uninitialized memory when running the pocket placer. * Added the ablity to draw tracks and obstacles with menus in the translator and added load of tracks to the icdrawd shell script. * Added missing twvias pseudo Tcl command. * Now recursively scale menu windoes so that fonts are properly set when the user requests a font change. * Added the font size editor to the iconbar to make life easier to change fonts. * Added the route usage report file, namely, the .route_usage file which shows the details of the last congestion route. Version 2.0.1 m : June 25, 2021 ======================================================================== * Added the output of the .pocket file which describes the row row groups and their ids. This file is created in the .../place/output directory as it is a product of the placer. * Fixed an incorrect initialization of the emptiness factor in the new pocket placer algorithm. * Added orthongal tracks spacing to describe tracks easier and more convenient. This feature was also added to vias and repeater objects. * Fixed a problem with pocket placer sometimes overfilling a row during congestion optimization. * Now immediate messages are displayed in normal message mode as they should. * Added the congest_equalize_rows option to the placer so we can turn off the original pocket placer algorithm. * Fixed problem with incorrect error messages on restore when prerouting exists. * Added the twgroup command which allows restart of a previously optimized congestion routing placement. This command allows any or all groups to be optimized if congestion routing has previously been run. * Added new congestion code which minimizes the number of cells in the the overflow group instead of trying to equalize number of cells in each group (congest_equalize_rows). This is now an option. * Added the ability to change routing width during the route of a single net in the detail router. * Added missing string conversion code to twpython. Version 2.0.1 l : June 7, 2021 Version 2.0.1 l-o : June 4, 2021 ======================================================================== * Fixed problem with ALIAS not being output on translate. * Got rid of debug print of points during translation. * Added track unit defintions which supports generalized vias and repeaters in order to support many future forms of routing including gridded, segmented, and taponly tracks. * Fixed a long standing bug during model creation which results in the boundary being incorrectly offset. * Removed design specific debug statements in placer. * Added ability to filter output vias and set the DEF output scale from a TCL script. * Added the ablity to control whether a pin can be skipped during detail routing. * Added the -report option to net_max_pinsize Tcl routine. * Fixed problem with assuming all designs have layer ALIAS rules which caused a crash in all programs. * Added more support for drawing vias and tracks correctly in the translator for debug of track and unit track definitions. * Now we don't store a placement as best unless the rows are not overfilled. Version 2.0.1 k : May 28, 2021 ======================================================================== * Fixed crash due to previous ichierarchy::flatten version so that even improper data does not cause a crash during netlisting. * Added the twmodel cleanup command which fixes the root cause of the ichierarchy::flatten crash. This command removes any invalid references to deleted models. * Added special net processing to the common net display tools found in all tools supporting graphics. It makes it easier to turn on and off globals and I/O nets. * Added the twnet rowgrouproutes command to the placer so that it is easy to display nets that leave their row group. * Made setenv.sh backwards compatible with old Bourne shells. * Added support for disjoint boundaries as a new floorplanning option. * Fixed a problem which errorneously reported problems with track horizontal lines as not being on the correct horizontal line. Problem was due to wrong internal scaling factor which was hardcoded. Now generalized and flexible. * Fixed a crash in the floorplanner when a wait state is issued before the floorplanner command. * Now placer runs in flat mode when user requests fast placement. This does improve the result for these fast runs. * Added the ALIAS layer AS another_layer rule to the design rules set to allow easy remapping of layers. * Fixed incorect warning of bad row lengths when in gate array or allow_space modes as the code was using the wrong field. * Added option to the parameter file to control final detail routing of the design thru placement. The default is off for detail routing but on for global routing duing placement. * Added a check for primary pin layer correctness if global routing is requested. It remaps pin to first routing layer if the pin layer is incorrect and output and error. The number of errors reported are limited to the first 100 errors. By remapping to layer 1, the global router can complete. * Now the congestion router handles empty spaces properly. In addition, the row group recognition code now handles rows of different lengths properly. Congestion optimization with not be performed if the constraints are already satisfied. * Added back icdrawr and icdrawd scripts which were accidently removed from the distribution. Version 2.0.1 j : April 13, 2021 ======================================================================== * Fixed problem with ichierarchy::flatten command which was causing a syntax errors because the original model if not referenced should be deleted. * Reorganized memory so that placement router uses less memory. * Found and fixed problem with extending tracks which was corrupting the number of tracks available in a region inflating them outside the region wires and keepouts. * Added a mechanism for saving and restoring the best overflow solution found during the execution of the pocket placer. Version 2.0.1 i : April 9, 2021 ======================================================================== * Added support for REGION WIRE constraints. * Now automatically detect when there isn't enough row length for the placer and add row length to the main set of rows. Previously, this was causing the placer to not find a very good solution. * Rewrote show_flows so that it is a Bourne shell and not a Cshell script. Version 2.0.1 h : April 5, 2021 ======================================================================== * Added user control options for congestion routing namely: congest_cap_derate, congest_wire_factor, congest_overflow_factor, and congest_emptiness factor which all have default values. This is the first version of the congestion optimizing placer which passes the first two benchmark circuits. * Added congest_route which is a future feature for congestion routing and is currently turned off by default. * Added twassign so the user can manipulate assignment statements at both the global level and the module or model level. * Added the -copy_assigns_to_tw option to the hierarchal flattening so that there is a record of assignment statements if necessary. Version 2.0.1 g : Jan 22, 2021 ======================================================================== * Fixed problem with twpadgroup commands and Tcl escaped names. * Added the twnet bus list command for convenience. * Added a site-package directory for the Python build so that we can supply a small set of packages as a convenience mainly networkx which is very useful. The setenv.sh and setenv.csh scripts were modified accordingly. Version 2.0.1 f : June 17, 2020 ======================================================================== * Temporarily removed advance code which was causing crash in the placer. * Added the ignore_layers and nomerge_layers options to the placer so we can properly process purpose pairs. * Added the missing -unique option to the twnet binding command. * Began integration of global router to the placer through use of common code. * Fixed a problem where track extension was performed on the wrong rows. * Reworked Python structure so that one can install multiple Python versions if necessary. * Upgraded to Python 3.8.4 Version 2.0.1 e : June 17, 2020 ======================================================================== * Fixed problem which prevented the placer from obeying the row length constraints when in cell under array mode. * Added the twtrack simplify and twtrack extend functions to manipulate tracks in a script. * Added the twrow group and twrow update commands. * Added the twgeometry inverse Tcl command to aid user coordinate transformations.. * Added support of graphics_position_invert in the parameter files of the floorplanner and detailed router to support KiCad. * Fixed a problem with the inverse orienation calculation when the orientation is 7. This function is rarely used by is used by some translation programs. * Fixed a low level algorithmic mistake which rearranged hash table lists on a resize. Now all tables remain their original order on a resize. * Now the igp floorplanner does not complain about a memory error when all cells are fixed. * Made it easier to see disabled entry widgets. The previous color #a3a3a3 is too light for easy viewing. Changed to #616161 * Added support for user model attributes. Useful for storing properties for general translation. Added the Tcl command twmodel user_attributes to support this new feature. * Updated the compactor in the floorplanner so we can do true 3D compaction. * Added ability to change instance version from Tcl specifically the twinstance Tcl command. * Added ability to create new model versions from Tcl. In addition, now you can reference models by using the construct [list $model $version] in the Tcl commands. * Fixed a long standing bug in the floorplanner which was causing more overlap than necessary. Added missing moves so the floorplanner has a more comprehensive move set. * Added the -model option to the twinstance get command so that it will return model and instance information for convenience. * Added the -simple flag to the twlayers direction command and fixed problems returning diagonal layer information properly. * Added the tracks grid extract command and implemented the delete all tracks command. * Fixed the annoying problem with the latest version of Tcl and the background popup widget which was not registered with the window manager. Now it is now long difficult to find in the window stacking order if it get blocked. * Added track checking design rule to make sure route stays within a track. * Added circular pad design rule checking. Added crude support for circulars pins. * Added -via option to the twtranslate icpin addport command which was missing. * Consolidated read/write placement file functions in to a library so all programs can share the same code. Version 2.0.0pre45patch2.tgz Apr 30, 2020 ======================================================================== * Added sanity check to load_checker to see if the input pin directions make sense. Now tool won't run in Y pins are inputs. Version 2.0.1 d : Feb 21, 2020 ======================================================================== * Fixed problem with missing Tcl library variable in libitools_dset.so. This was due to upgrade to Tcl version. * Fixed problem with new keepout definition code. Now we only initialize once. This was causing the generation of nan values. * Improved the efficiency of the cell compactor when the user accidently gives us overlapping fixed obstacles. We ignore them rather than generating a useless constraint in the compaction graph. * Fixed a bug in the Tcl that prevented fix instance GUI from working on macro cells. * Added ability to ignore local interconnect and avoid creating tracks. If a track is created on local interconnect, it would go too far and be a design rule violation. Version 2.0.1 c : Jan 29, 2020 ======================================================================== * Added -glob pattern option to twmodel get command for convenience. * Added suport for TRACKS in the placement program. * Fixed problem with the placer hanging on small number of cells and rows. This was a problem pin the rare site code. * Improved the sizer so that it can flatten models efficiently which is useful when routing designs. It now can be called from either the translator or the detailed router. Memory leaks have been eliminated. * Added the ichierachy::flatten command which calls the sizer to flatten library models. * Added the ability to search layer names using wildcards in layers GUI. Version 2.0.1 b : Dec 4, 2019 ======================================================================== * Fixed version menu due to Tcl/Tk update * Fixed exit popup due to Tcl/Tk update * Fixed size of install box due to Tcl/Tk update * Fixed problem with itools_tktable version due to Tcl/Tk update * Now congestion placement program does not overflow even on fast mode. * Added routing of congested placement aware problems. Uses contour router to start. * Updated the view manager so that it searches properly once again. Version 2.0.1 a : Dec 4, 2019 ======================================================================== * Updated to Tcl version 8.6.9 * Updated to Tk version 8.6.9.1 * Updated to Tix version 8.4.3 * Updated to Expect version 5.45.4 * Updated to htmldoc version 1.9.7 * Improve congestion analysis program so that target areas do not overflow. Version 2.0.0 pre48 : Aug 14, 2019 ======================================================================== * Fixed problem with string manipulations when strings are strimmed bu adding missing EOS. * First version where Python interpreter can read back Tcl integer objects * Added main group determination in congestion analysis placement algorithm. Version 2.0.0 pre47 : Aug 14, 2019 ======================================================================== * Experimental support for Python. Under development. * Added routing obstacle extraction. * Added better traceback capabilities on crashes * Added ability to recalculate timing constraints in Tcl * Added path comments so user can understand where constraint was generated * Updated the neighborhood constraint generation so that it reflects how hard it is to meet a neighborhood constraint. * Added net_reporting option in the placer which turns off net information which can be overwhelming. The default is to report net status. * Added default_padside option to the placer. * Added -warn_port_mismatch option to Verilog parser. This allows user to control the warnings which previously were excessive. * Now we load all tw* and ic* commands and namespaces when executing the list commands option. * Improved the functionality of the tweditobj commands so that all commands now have the -global option to automatically calculate the global position. All objects work properly except arcs which still needs work. * Added the draw die and draw core menu items to the placer for better user debug. * The die drawing routine now is semi transparent for better viewing. * The placers now report the dimensions of core, padring, and die. * Fixed a problem with pad side determination in the gate array placer. Version 2.0.0 pre46 : April 17, 2019 ======================================================================== * Fixed several problems where bad data would crash the placer and translator. * Fixed a problem in placer initial configuration algorithm. Version 2.0.0 pre45 : March 19, 2019 ======================================================================== * Added error and warning file support to the translator to help deciphering error messages when log file is large. * Now we tell the user the coordinates of overlapping cells in the placer. * Improved the quality of the result when spares need to be placed and all cells are fixed. * Augmented the arc and drawing routines to include the missing line width option. * Added the ability to turn off inversion of graphics drawing system for debugging purposes thru the new "twposition invert" command. * Rewrite of the tweditob code to include missing circles and added features to facilliate debugging. * Found a long standing bug in the GDS2 translation code. Previously, only orthogonal rotations worked properly. Now all angle rotations work properly. Added the -angle option to twgeometry transform so any angle transforms can be used in Tcl scripts. * Added the twgraphics_context frame command to the translator so the user can set the drawing frame if desired. * Added the ability to draw sites in the floorplanners for debug purposes. * Fixed problem with iflow program reporting add_flow_tcl_cmds that it can't find $icdirG * Now placer issues a warning and not an error when it detects an infinite loop when there are only spares to be placed. Version 2.0.0 pre44 : March 19, 2019 ======================================================================== * Fixed problem with clustering program exiting when data errors are present in the design. Now we try to return a placement if at all possible even the presence of cells that are two tall for a row. * Improved the placers internal algorithm for removing overlap in the allow_space or gate array mode. Previous version was inefficient and did not handle vertical rows. * Fixed problems with gate array mode ECO mode and pad placement. * Now make sure to pass SPACER models to the library. * Added the draw die option to the placer for debugging. * Added a better message for off the grid warnings. * Improved the quality of the gate array placement in fast place mode. Version 2.0.0 pre43 ======================================================================== omega20z9: Feb 25, 2019 * Fixed a crash in the LEF write when model boundary information is not found. * Added the twdraw lef_units command and added the use_lef_scale option to the twread_lef command. omega20z9: Feb 25, 2019 * Added the -E switch to iplacesc to handle whether errors will be displayed graphically. * Added a better error message when a cell does not match any row criteria. Now we put this cell in row 1 to avoid any possible problems with crashing due to a lack of row assignment. Previous message was cryptic: ERROR[unlap]:instance <> does not have a block assignment. * Added the ../tcl/twflow directory to allow the use of Tcl scripts in flows. * Added the twflow graphics_errors Tcl command to allow twflow scripts to find out the state of the graphics error command line switch to twflow and allow the user to set it in a script. * Added ::twflow::suppress_graphics Tcl command to placer's argument list so that in batch mode we can properly suppress the evaluation of errors using the graphics popup dialog box. * Added ability of the twflow program to evaluate Tcl commands in its program argument list. * Fixed problems with installing multiple OS versions due to name change. omega20z8: Feb 5, 2019 * Added the schematic_ordering feature to the placer. Schematic ordering looks at a placement and determines where the outputs reside. If forward is requested, outputs should be to the right (and top if a vertical row). In the reverse mode, outputs should be lef (and bottom). This only is in effect when the I/O pins are ignored; otherwise wire length calculations will override this option. * Added the twnet ignore_pin state command to inspect the ignore state of I/O pins. * Added the ability to ignore LOOK and LADMIN data from the license statistics command. In addition, we added ability to send XCEL information to stdout or stderr. omega20z7: Jan 7, 2019 * Added power domain isolation feature which puts even the default power domains in a separate power domain. * Fixed problem with program reporting errors when there were none. * Fixed memory leak in power domain optimization. * Improved the quality of the power domain optimization row evening code to include non power domain rows. * Fixed problem with power domain optimization when timing constraints are present. Previously, it would crash during the dual. * Added sqlite3 package as a loadable module for database capabilities. * Fixed problems with itranslate model editing. Now the edit switch properly allows the ability to measure model data. This was due to improper epsilon scaling. * Added the measure pitch command to the itranslate view model mode. * Added the -force width mode to twmake_default_feedthru command for convenience. It allows the creation of a feedthru of any size. omega20z6: Sep 25, 2018 * New auto row evening algorithm which takes wide cell statistics into account. The new algorithm works well for designs which have wide cells relative to their row lenght. * Added the twstatistics function to the placer to gather info for the new auto row evening algorithm. * Updated the ICTk argument switches so that arg shift works properly when using -A and -- as commonly used. * Added the ../tcl/place_cntrl/roweven.tcl Expect script to build a unevenness report on a set of placement runs. omega20z5: Sep 24, 2018 * Added row evening code to the power domain algorithm and fixed problems with vertical rows when performing power domain optimization. * Added the -nocompactrows options to twwrite_ic command so we can support the output of "twswap_coordinates design" command properly. * Fixed problem with processing vertical rows when performing the removal of unlap. * Fixed crash in Tcl commands when user tries to output an empty design. Now the proper error messages are given. * Fixed problem with typo in ENDPOWER keyord as it was missing a space and causing a syntax error. * Fixed problems with initializing vertically oriented cells. * Added the twswap_coordinates design command in the translator so that it properly converts from horizontal rows to vertical rows and vice versa. * Added the -stats option to itranslate exit command for more info on program execution. * Added ability to concatenate LEF files. omega20z4: Sep 6, 2018 * Added missing code which was causing placer to crash during overlap removal. * Added better support for GCELL processing. * Added code to automatically extract pad vectors. * Added code to enable fine control over DEF input and output. * Added ability to change context while in the floorplanner doing row topology commands. This is a better way to do the post rowgen Tcl command as it is much more general. The post rowgen function still remains for backwards compatibility. * Fixed problems with pad and padgroup names in Tcl commands when names were Tcl escaped. omega20z3: Aug 22, 2018 * More changes to prevent crashes during power domain optimization. omega20z2: Aug 5, 2018 * Now all programs read the .seed file if it is present. * Modified so now all tools read the .seed file if it is present. This allows easy setting of the random seed to all tools for easy reruns omega20z: July 26, 2018 * Major work performed on power domain optimization. This version does a two stage primal dual optimization. This is the first cut to allow user defined class constraints. * Better support for user defined colors omega20y: May 18 * Updated the power domain optimization code for double height cells. * This is a testing version for the power domain optimization. * Fixed a problem where included files that were specified relatively got the wrong fully qualified pathname when parsing files. * Added twpad, twpadgroup, and twgrid commands to the placer TimberWolfSC. * Updated icabstract::library_models so we can build square cells for exploratory placement work * Added the -padsonly options to icmodel_data Tcl procedure. * Fixed problems with linear assignment code when solution is close to machine epsilon. * Fixed problems with wrong coordinate for the exact pad constraints. Added loadpos and unconstrained options to the icpad Tcl command. omega20x : Feb 27, 2018 * Fixed problems with clusters in hierarchical mode when double height cells are present. * Fixed a problem with double height cells having overlap in allow_space mode. * Improved the detail router so that the fast meta routing heuristic now supports the hybrid router. omega20w : Jan 30, 2018 * Now prevent a crash in the overlap code if something goes wrong with a user row assignment. * Improved the efficiency of reading in large subcircuits during netlist processing. * Now power domain constraints are glob aware, that is, the user can use the wildcard * in the name of the instance. * Fixed problem with mistake in wire length calculation in translator. This was only an informational mistake and not used in any calculations. * Added a support for an explicit shared boundary layer. * Fixed problem with adding an offset to the original library geometries when translating data. * Fixed a long standing issue with message formatting when long string ares present. Now we properly word wrap. * Added via_messages keyword to turn off via messages during read of parameter file. * Updated the sizer output model functions so we can process cell overlap properly. * Added ability to draw power domains in translator. * Fixed a crash in placer when strict overlap removal is performed on complex row definitions. * Fixed a problem with the detail router when expanding virtual channels. * Fixed a problem with the scaling formatting function that would add an extra blank space to the output of a small floating point number like 0.1. It resulted in Tcl commands returning { 0.1} instead of 0.1 * Added better error message for the "icmodel type" Tcl command. * Updated the parallel read code to handle multicore hosts. Now processors with powers over 1 are treated as multicore processors properly. * Added the -unique flag to the twinstance Tcl command so the we can build netlists properly when cells have multiple bindings. * Added the -glob flag to the twnet get Tcl command so we can search net names conveniently. * Added the ability to maintain the bus structure of a netlist for use during placement and routing thru the VECTOR constraint. * Initial version of power domain primal/dual method to configure where to put power domains. * Added support for multiple planes in the floorplan row configuration tool. * Now a shared boundary can have a more complicated sharing code which includes upper and lower classes so that a wider class of sharing can be implemented. In addition, a single number can be given for each edge for convenience. * Implemented new algorithm for power domain optimization. * Updated the gate array code to handle 3D sites. omega20u : Jul 25, 2017 * Initial power domain definitions for new power clustering algorithm. * Fix for unlap unable to place message. Now a warning. omega20t : Jul 17, 2017 * Added icnet cost and icnet numpins to the translator as they are useful commands. * Very clean implementation of overlap removal algorithm. * Now added a new "warning" option to the require_vias parameter. Now via problems are not reported if require_vias is set to off. If the warning opttion is selected via problems are all reported as warnings regardless if they are truly errors. In the "on" state, all messages are properly reported. * Improved the overlap tool interface so you can independantly chose errors and warnings. * Improved the graphics drawing for fixed cells in the placer. * Rewrote the XML library interface so it works and compiles properly. omega20s : Jun 16, 2017 * The overlap removal code works properly for unconstrained cells. Next up constrained cells. * Added ability to write just the discovered spare instances to a file. * Added the icmodel add_delay and icmodel template commands for processing timing arcs properly. * Added the sequential attribute to standard cells. Improved the reading of Synopsys library files. Added missing normalized_voltage variable support for Synopsys .lib files. * Added model field to ZSA report file to make it easier to understand. * Fixed problem with old Synopsys parser which barfed on a long comment. * Added -quiet switch to icflatten_netlist * Now quiet an error in the translatore when no vias are given. * Significantly sped up the placer when 3D ports are present. * Changed name of iplacesc to TimberWolfSC. * Fixed infinite loop in ucluster when a design has very little connectiveness. Now we insure that we cluster a reasonable number of cells to avoid the infinite loop. * Increased the default number of block classes to 1024 * Added initial support for 3D placed standard cells. * Now we tell user when run height is exceeded during construction of clusters so that input data errors can be discovered easier. omega20r : Apr 11, 2017 * Updated EZ native GUI so that the packing and resizing is correct. In addition, Javascript loading of EZ now may be relative to the URL. * Now make sure we don't duuplicate signals during output of non-clustered cells. This was causing an abort during placement. omega20q : Feb 27, 2017 * Added error checking for gate array placer when number of pads exceeds the number of pad sites. * Improved the hierarchical placer when in gate array mode with sites. * Updated for new TimberWolf logo. * Added ability to maintain and detect unique object ids to the iceditobj command. In addition, now iceditobj clear works properly. * Added DIE restriction constraint for 3D placement. * Added icinstance goto command which performs Goto relaxation. This option has been added to the Edit Cell graphical menu. omega20p : Dec 27, 2016 * Added tcl command "icinstfix type" command as well as a fix to the locations returned by the icfix_inst get command. In addition, added the icinstance invalid command to see if a cell has a valid neighborhood constraint position. * Added the iterate feature to the row-based placer. Now user can specify how much they want to iterate for a good solution. omega20o : Nov 8, 2016 * More overlap removal fixes. Almost working version of vertically placed rows. * Update of install process to account for name change back to TimberWolf Systems, Inc. omega20n : Oct 25, 2016 * Fixed a crash when removing overlap for cells in vertical rows. * Improved the behavior of removing overlap for vertically placed rows. * Improved the handling of multiple height cells. Now we round to the closest number of rows. Cells which were only slightly over two rows were being set to 3 rows. * Improved the drawing of neighborhoods constraints. * Updated row processing of double height cells. omega20 : Sept 21, 2016 * Added support for vertically oriented constraints to the clustering program in the hierarchical placer. * Fixed a problem with processing neighborhood constraints. Internally, tool was translating position of neighborhood. * Fixed a problem with removing overlap of rigid neighborhoods in the left_justify mode. * Fixed problems with graphics redisplay of high lighted cells. * Fixed crash when high lighting an extremely large number of cells. * Added unlap_max_checking to the placer to due exhaustive error checking. Off by default. * Now the default for the instance overlap checking tool is error instead of undefined. * Prevent a crash when attempting to get fixed information for an instance using Tcl that doesn't have any. * Added ability to draw neighborhoods in the placer. Added preliminary import placement option into placer. * Now vertical clusters are output properly in the .pl1 file. * Fixed a problem with the initial placement of a rigid_neighborhood when all cells are in a horizontally placed neighborhood. * Now the placer tries to improve the result of a restored placement. This improves the result slightly and fixes a problem with overlaps. * Fixed problem with rigid neighborhood constraints in the placer. * Fixed a problem with the spare instance cost in the placer. * Now the check overlap code looks at layer information so now overlapping pads are ok as long as they are on different layers. * Now Write Placement File works properly in the placer. * Improved multi-tier processing. Improvements to initial placement algorithm in the placer. * Fixed edit cell fixed instance button so it displays properly when a cell has a neighborhood constraint. * Now fixed neighborhoods are by default lower left, upper right corners instead of center referenced for ease of use. Fixed problem where neighborhood constraints would disappear. * Now the report supports reporting multiple cell names for multiple drivers. * Now missing models are errors when processing the load check files. If models are missing, it will activate the graphics view so the user can find the missing models easily. * Fixed problems with creating unusable port topologies when call the port_shift funtion in the placer. * Fixed problems with creating multiple binding errors in the placer when user defined clusters are present in the design. * Now missing via layers are warnings rather than errors in the case that detailed routing is not requested. * Reorganized and simplied placement graphical menus to include Tools and Highlight to make it easier to find desired item. * Added the Write Placement File and Snap to Rows menu items to the translator. * Now the translator has a snap instances to row function. * Added ability to remove overlap for multi-tier cells in the translator. * Added ability to create dummy Verilog primitive cells. * Improved overlap removal of multi-tier cells. * Now only the placer reports global nets and ignored nets instead of every program. The output is now prettier and less confusing. This eliminates the bad_net output messages that previously existed for unused global nets. * Fixed a problem in the translator when building a hierarchical netlist. Previously, at high levels of the hierarchy it failed to look at the proper pin list which resulted in bogus error messages. * Now the signal binding errors are handled so that all of them will be reported before an exit in the translator. * Fixed problems with clusters with a fixed orientation in the placer. It was outputting an error message about pin topology being in error. * Now the translator can draw simple clusters. * Updated the global router to handle designs that have very very small manufacturing grids. * Fixed a crash in the placer when allowed space is on and ports are present. * Major rewrite of model hierarchical display widget in translator and placer. * Now the prerouting extractor has the ability to calculate global coordinates. Previously, it only handled model coordinates. * Improved the ability to display hierarchical data in the translator and placer. * Now too many error or warning messages now generates a warning rather than a surpressed error message to make it easier for user to search for real errors. * Fixed a crash in the placer when permutable clusters are present. * Finished code to extract internal prerouting. * Added the -allpins option to the icinstance pin Tcl command. * Got rid of bogus error message when cluster is not permuttable. * Now cluster display in the placer is persistent. * Now we adjust the number of clusterable standard cells to account for user defined clusters. This was causing hierarchical placement mode to be called when there wasn't enough cells. * Added the ability to control the orthogonal overlap threshold in the overlap instance tools. * Now we don't allow ports to be spare cells as they are not standard cells. * Now we calculate the split cluster cost properly for complex or split rows. * Prevent a crash due to clusters and spare instances. A spare cell put in a cluster now does not cause an attempt to call the spare cell placement code. This was causing a crash and the generation of many error mesages in the placer. * Added the icrow rcolor and icrow rclass commands to handle complex block signatures. * Added the icgeometry enumerate all command to make it easier to search all layers of a geometry object. * Rewrote the GDS2 library processing routines to use the updated tile database code. * Added the icsignature complex command so that the user can determine if a block signature class has conflicts with another class. * Fixed incorrect error message in the cluster program which was causing placer to stop prematurely. * Fixed problem with the license server only reporting detailed information on the last program being checked out. * Added an overlap remove and analysis tool into the placer similar to the one in the translator. * Fixed a crash that occurs in the placer when just cluster cells exist in the design and they need to be split to satisfy row constraints. This crash occurs when path constraints exist at the cluster level. * Now block class signature initialization occurs before random placement in the placer. It is now much easier for the user to see if the random placement algorithm is working properly. * Fixed problem with a spare neighborhood constraint not being adjusted for the proper block constraints. This resulted in many spares being out of their proper rows. * Fixed crash in the placer due to neighborhood constraints during initialization. * Added the -instance option the icmodel wires command to support internal prerouting. * Added the -rects option to the icinstance pin command. * Rewrote the clustering code to simplify and to add vertical clustering. * Added the -all option to the load checker report. Now the default is to remove all constraints which were set to zero. * Fixed problems with placer's graphics highlighting functions. * Improved the off grid warning messages in the placer. * Now the default gridding check is bottom left edge of standard cell. * Added icrelated command to placer. * Added icgenrows site_width and extra_columns commands for gate array mode. * Fixed bin packing algorithm in the gate array placer. Now it can place in the minimum amount of space without the need for extra spacers. * Corrected the problem with calculating the number of sites in a row in gate array mode. * Now the strength of path constraints can now be set from Tcl. omega19 : Apr 25, 2016 * Fixed problem with crash in floorplanner compactor when fixed cells were present. * Fixed an infinite loop in the placer when datapaths are present with multi-tier instances. * Added the coreinstance option to the floorplanners to handle user generated core regions. * Fixed problems with floorplanners reporting a vertical tile when everything was fixed in a design. * Added the -nomemory option to the icgenrows update Tcl command of the floorplanners. * Added the Recalculate/Update command to the row toplogy code of the floorplanners. * Added the ICFP*coreinstance option which allows the user to define the area for row generation. This is usually specified as a cover cell. * Fixed problem with datapath graphics not showing up due to mistake when graphics surpression was added. * Now we ignore cut warnings if technology is not required (not routing) * Improved multi-tier placement. Now works up thru random placment. * Fixed a very bad bug in the placer which was preventing ECO from annealing. The mistake has been present since 43u. * Added overlap detection and verification tool to translator. * Added path constraint viewer to the translator. * Now we tell the user the program is busy when they type in a command in the graphics mode. * Now the compactor will not try to move fixed ports as it was incorrectly doing previously. * Now the port/switch/option algorithm automatically detects the ports layers in the cells and reports what it found. The compactor was modified so that it understands all of the layer interactions. In addition, fixed ports/switches/options are now detected properly so that they are not included into the compaction process. * Added the -limit option to the icpath Tcl command and also added the strength field for more information. * Fixed problems with port or switch compaction taking an extremely long time when ports with two layers in them were detected. Introduced a new port layer signature algorithm which builds sets of ports with the same sets of layers for efficient processing. Previously, algorithm took hours and now it takes seconds. * Added twgraphics::status command so we can set the proper status signal from Tcl commands. Now the translator shows busy during a read of a state such as Placed. * Added the icnet paths Tcl command to return the length constraints that have been added to a net. * Improve the handling of the display of row class constraints and their instances. Added Tcl procedure highlite_inst_classes to the set of routines. Needs to be added to a menu. * Added the member_flag argument to icinstance::class_insts Tcl command so that we check either exact matches or complex matches. * Added the twgraphics::open Tcl command so the user can easily check if graphics are on. * Now the bin packer in the placer works by placing cells with the most restrictions first. This specifically targeted designs with instances with row class constraints. * Fixed a problem in the placer with cells with row class constraints jumping out of their rows. Also added a verification tool in the placer and translator so the user can verify that all cells are correct. * Fixed a problem with the placer erroneously generating obstacles in the wire length calculation when none were present. This manifested itself in the load check where the length of the path was in error. * Now multi-tier cell code is more robust in the placer. Multi-tier placement works now for the simpliest cases. Complex row code still needs to be added. * Now prevent a crash when the color of an object is erroneously set to a color index of 0 internally. * Added the -pins options to the icnet bbox Tcl command so one can find the pins setting the bounding box of a net. * Added more capabilities to the icpath Tcl command including the ability to generate a .pth report in the placer and translator. * Added icinstance checkclass command so we can check to make sure that instances with block constraints are properly placed. * Fixed problem with load check report file. It generated erroneous output when paths are weighted. omega18 : Mar 7, 2016 * Now load checker and paths support weighted paths correctly. * Prevent an unnecessary and wrong error message when processing paths containing TimberWolf generated nets. * Prevent a crash when fixed cells are placed impromperly in rows. * Fixed a problem with generating the constraint value for softgroups. Previously, it was generating too large of a constraint. * Better messages for overlap detection in the placer. Now no longer limited to 100 messages in the error file. * Added the .errors and .warns files which contain just errors and warning under the place directory to make it easier to see placer problems. * Added a better color support for shared boundaries. Now shared boundary color is in aquamarine for better visualization. * Added preliminary support for cell overlap visualization in the translator. * Fixed major problem with weighted path constraints. Now cost is properly calculated. * Fixed output problems in the .pth file with respect to weighted paths and error percentages. In addition, the weights are calculated properly. * Added support for the .errors and .warns files which contain only the errors and warnings of the placer program. * Now give a better explanation of where the messages (which subroutine) are quieted. * Added wildcard ability (glob function) to SOFTGROUP constraints. omega17 : Feb 10, 2016 * Fixed problems with load checking report generator. Was aborting due to and uninitialize netname variable. * Now we no longer try to split a cluster with only one cell in it. This was causing a crash in the hierarchical placer. * Fixed a bug introduced into the placer in version omega date March 16, 2015. * Fixed a crash in placer that was created in omega16 when complex row processing was added to the placer. * Updated cluster program to go on even when block lengths don't match and to understand vertical rows properly. Previously, it was not able to create the proper clusters and huge number of errors were generated. Now it scales the number of clusters by the actual length of the cells or the total row length whichever is larger. If clusters are in short supply, now we don't output empty softgroup clusters. * Updated cluster program to handle vias properly. While it did place correctly, it was outputting hundreds of annoying error messages. * Prevent a crash when processing fix neighborhoods. * Prevent a crash when processing vertical double rows in the placer. * Now we always calculate the block class signatures. * Now we handle vertical rows properly when we process blockages. * Added the icfix_inst set BLOCK y command for placing cells in vertical rows. * Fixed problems with adjusting fixed cells in vertical rows. Was aborting syntax checker. * Improved the handling of multi tier cells. Now multi tier cells can exist in complex row configurations. Fixed a crash in the placer due to multi tier cells. * Fixed placement problem when multi tier cell is placed in orientations 4 thru 7. * Fixed problem of the placer putting multi tier spare cells into neighborhoods when they are fixed by the user. * Added ability to highlight a row in the placer. omega16 : Dec 22, 2015 * Now the print table Tcl function can take a string of any size. Previously, it would exit the program (for example the translator) if string exceeded 16k characters. omega15 : Dec 7, 2015 * Fixed a problem with the last stage of the placer. Low level swap function was not storing the proper orientation so the final result was suboptimal. omega14 : Sep 22, 2015 * Improved the softgroup constraint code so now it reports when it is overconstrained and aborts if too many cells are fixed. Improved the clustering when the placer is in hierarchical mode. * Improved the timeout feature in the placer. Now when the timeout occurs, the annealing loop is exited as well as the greedy solver. Previously, the greedy solver was run till completion. * Updated the icwirelength command in the translator so we can make an initial wirelength report. * Updated cell neighborhood initialization code in the placer to improve initial neighborhood placement. * Now we fixed problem with icnet driver command accidently returning the pin type. This problem broke the load check Tcl code. * Fixed the syntax problems when cluster names were numbers. Now they are treated as strings. * Added more options to the icwirelength command in the translator. Added -xy, -unscaled, and -place_cons options. omega13 : Sep 22, 2015 * Now we write out any softgroups if they have been defined in the translator. This will allow the user to put softgroup constraints in the itools.con file. * Fixed problems with outputting softgroups in clustering program. This was causing a syntax problem during hierarchical placement resulting in an incomplete placement run. * Fixed crash due to freeing internal data twice in the placer when the allow_space overlap option is in place and there is a small row not large enough to fit any cell. omega12 : Aug 21, 2015 * Now the placer properly handles switches that need their orientaion rotated by 90 degrees. * Added softgroup processing to the placer's hierarchical mode in order to improve the quality of the placement of soft groups. * Prevent a crash in the placer when soft groups are not specified properly. * Updated EZ documentation to ad description of wires. omega11 : Aug 4, 2015 * Now we no longer call the port compaction algorithm in the placer if all ports are fixed. In addition, we added some messages in the log file to tell the user the number of ports and moveable ports. * Fixed problem with cluster program increasing the size of the variance but without the algorithm converging. omega10 : Aug 4, 2015 * Now we give the user more info about the size of large blocks which span rows imperfectly. * Now placer gives more info when listing soft groups in graphics mode. * Now we prevent a crash when a keepout is not defined properly. * Now prevent a crash in the placer when row assigned to a standard cell is zero. * Now we check to make sure that only row-based cells are present in clusters. * Now the placer properly return the error code when in hierarchical mode. * Fixed major problem in hierarchical mode where clustering program was trying to cluster large hard macro cells. * Fixed problems with the Tcl print table when the size of the column is greater than 2048 characters. Now each column is dynamically allocated and there is no size limit. * Added the -core and -sort size options to the icinstance get Tcl function. * Added justification support for the Tcl table library module. Valid states are left, center, and right. The default is right justification. * Now the load checking report is able to properly report the hierarchical names of clustered instances. * Added the icinstance cluster, clusterpin, and isacluster to support looking up clustered instances and returning their hierarchical name. * Now missing padside information is only a warning in the translator. * Added the icsignature Tcl function in translator and placer to manipulate block classes. * Added the icrow_stipple variable to the placer. In future versions all tools will have common variable for setting the appearing in the graphics mode. * Added the ability to visualize row class definitions in both the placer and the translator. * Fixed a shortcoming in the prerouter extraction algorithm which was naming all of the ports the same causing problems for global routing. * Now icinstance class returns the proper default class which is zero. * Added the icredraw event command so that we can see immediate update to graphics events when we write GUI scripts. * Major improvements to iplacega which will also now be know as its original name TimberWolfGA. Upgraded the site processing ability and added a better site visualization tool. omega9 : June 25, 2015 * Added twgraphics::supress routine so we can suppress graphics in Tcl scripts. * Fixed problem with strict_row_control now working near the end of a design. * Added ability to rraw soft cells in both the placer and translator. In addition, added the ability draw all of the cells connected to the highlighted instances. * Now translator can draw multiple instances when highlighting and can show related instances. * Added ability to toggle cummulative drawing of soft groups in the placer. * Improved the behaviour of soft groups. Now unaligned softgroups work well. * Now prevent a crash when user type in garbage into the graphics command line. * Fixed block class signature code in the placer so that it properly allocates block classes when some cells are assigned to the default block class. * Updated translator so it properly merges the results of multiple icread_par commands. * Now prevent a crash in the global router when a standard cell instance is not assigned a row. * Fixed problems with soft groups update in the placer. After iteration 120, the lack of an update caused either an infinite loop or crash. * Fixed permission problems on several files in the EZ and tcl library directories. * Now the default is for icread_vhdl to flatten the hierarchy after the read. * Now prevent a crash when using the VHDL reader. In addition, we removed the problem with creating a USER_DEFINED cell erroneously. omega8 : June 8, 2015 * Now we output a warning when the pitch of a layer is zero or negative. * Fixed an infinite loop when the user improperly has a routing layer with a pitch of zero. Now translator reports and error and tries to continue onward. * Added the ability to call the strict residual overlap algorithm in the placer when in graphics mode as it is now in a pulldown menu. * Fixed the problems with removing residual overlap in gate array mode and made a new parameter option called "strict overlap" which when on in standard cell placement mode will remove all residual overlaps if at all possible. This should be used with care as it can cause a jump in wire length if constraints are extremely difficult to meet. * Now properly restore a placment file using the icrestore command in the placer. Previously, some of the orthogonal coordinates (row coordinates) were improperly calculated for a multi high cell. * Now the translator returns a TCL error code when we encounter trouble with missing cells when reading the library using the icread_lib command. * Added missing code so that the uniform distribution of global spareinsts is effective in hierarchical placement mode. i * Fixed a initialization problem in the datapath extraction code. Was sometimes not obeying the minbit and minstage options. Improved the datapath extraction GUI. * Fixed a crash in the placer when multi-tier models don't line up perfectly. This was happening due to a bug in the clustering algorithm. * Fixed problem with missing default algorithm for the SOFTGROUP contraint. * Now we make sure we don't add multi tier cells to the row length when they are outside a defined row. This was causing inaccurate row length calcuations. * Added auto_row_length parameter file option. If enabled the placer will try to adjust the row lengths to match the amount of cells present. By default, it is defined for simple row topologies and off for complex ones. * Now prevent the placer from stopping too early when netlist has problems. In some cases, placer was not performing spare cell algorithm due to exiting early. omega7 : Apr 17, 2015 * Added preliminary documentation of SOFTGROUPS to EZ. * Added the ability to turn off the fly lines when viewing spare instances. * Now give a slightly prettier output when we output class aliases with conflicts. * Now we allow spare instances to have a small set of valid rows. * Fixed a problem with the algorithm for spare processing when gravity was specified. The spare cells were sometimes members of attractor object rather than being ignored. This should improve the behavior of small gravity objects. * Fixed a crash the was occuring in the Tcl command iceditobj when the user specified a bad color. * Added ability to sort by model in the Draw Instances widget. In addition, we can now sort increasing and decreasing. omega6 : Apr 8, 2015 * Added the ability to sort by name and case insensitive name. * Added the icdraw ignorepins command so we can avoid drawing ignored pins in the placer and translator. * Now prevent a crash in the placer when a multitier cell covers all of the rows. * Now icdrawd properly uses the draw mst mode so we view the nets properly. omega5 : Apr 8, 2015 * Fixed overlap problem in the placement engine. It occurred when there were complex rows. * Added initial Draw Instance to the placer and the translator. Needs Tcl work still but functional. omega4 : Apr 4, 2015 * Updated the load checker code so that it traverses the hierarchy in order to extend the load table. Now missing complex modules are warnings rather than errors if at their is least one connection below the module. * Added the icmodel::pintypes Tcl command to support the load checker. * Now we control the error and warning messages about multi tier instances which span the rows improperly. It is now only a warning when the instance is fixed. * Prevent a crash when a multi-tier cell is not placed properly in its row. * Fixed a crash due to missing code when there is a class signature conflict. Conflicts are supported even though they are not efficient. Now we give example of instances in each of the conflict classes for easier debugging. * Now prevent an infinite loop in the floorplanner. Added planar_route parameter option to tell floorplanner and global router that only one routing layer is present. * Made the flow editor accessible thru a shell script. Now you just need to enter flowER on the command line to access it after sourcing the ICDIR initialation files. omega3 : Mar 30, 2015 * Now the load_checker will extend the load table to include cells which are composed of standard cells. Fixed a problem with matching model names when searching load table. * Improved on the datapath placement algorithm. Now for folds greater than zero, the program costs the alignment properly, driving the datapath together. The only code missing for the datapath placer is the final alignment for folds greater than zero. (It has been done for folds = 0). omega2 : Mar 16, 2015 * Major improvements in row evenness due to new algorithm in placer. * Fixed several crashes when user data is incorrect. * Change the _io special suffix to _TWio so to avoid conflicts with real design names. * Fixed crashes in the placer when double height rows are not defined properly. Now the placer outputs reasonable error messages. omega : Mar 16, 2015 * Now report the unweighted wire length at the end of placement. * Added first working version of rigid algorithm. * Enhanced the placement algorithm with a new search mechanism which speeds execution especially when block classes are present. * Fixed problem with placer moving cells out of block classes when in hierarchical mode. * Added ability to add glob patterns when ignoring models in the verilog translator. * Changed the global spare stipple pattern so that it is easier to see large spare cells. * Updated the SOFTGROUP constraint so that it allows the RIGIDLY fixed option, now incorporates path constraints, and also allows folding. * Fixed problems with loading stipple patterns correctly. Was incorrectly returning error messages even though it had loaded correctly. * Added icnet delete and icnet reindex commands to facilitate datapath processing. * Added horizontal_wire_weightG to the placer for completeness. * Now the -e option to the syntax program is visible to the user. * Fixed a problem with rows being left empty and row edges being very jagged. This was due to a miscaluation in the row code. In addition, fixed problem with some block class cells leaving their class. * Fixed problem with cells leaving their proper block class. * Now we delete any keepout in the placer which fails buster verification so we don't generate hundreds of errors and prevent proper operation of compaction. * Now fixed constraints have priority over class constraints. Some multi-tier cells were moving even though they were fixed due to bug in class constraint processing. * Added the icspare isa and icspare hasgravity commands so one can determine from Tcl whether an instance is a spare and what gravity it may have. * Added the -glob, -nocase, and -id options to the icinstance get command so one can write glob type expressions for filtering instance names in addition to the regular expression capability which already exists. * Fixed an infinite loop in the placer due to incorrectly parsing I/O names. This occurred almost at the program after the annealing process was over. * Added the icdraw rows command to both floorplanning tools. Added missing icrow command to the ifp program. * Added the -nogenerate option to the icoutcons function of the floorplanners. * Fixed a problem with translating two hierarchy dividing characters in a row when translating Verilog. This was causing duplicate versions of cells with just the difference of one hierarchy character in the instance name. * Now the default hierarchy drawing depth is 0 or just primitive data in the translator program. Previously, it was all levels and it was a bit busy. * Now prevent a crash when the members of gravity are out of the universe. Also do not place hardcell spares. * Now we rearranged the order of the drawing so pins are on top when drawing datapaths in the placer. * Fixed a problem in the calculating the gravity neighborhoods for spare logic when the statistics are skewed, that is, when there are only less than or equal to one gravity member. This was causing an excessively tight constraint which was totally unintended. * Now the spare code is enable at iteration 101 when in clustering mode so that algorithm has more time to recover from any cost jump. * Fixed a bug in the cluster initialization algorithm when complex rows are present. Previously, this bug generated excessive overlap. * Fixed a bug in the clustering algorithm which was causing the wrong number of row class clusters to be created. This was causing hugely uneven rows. * Now surpress excessive buster_verify messages by now limiting them to 100 by default. User can modify behavior using .wlog file. * Added ability for user to specify the spare instance list. * Now prevent a crash in the placer when no cells are present in a row. * Fixed problem with initialization of cells that have neighborhood constraints during random placement. * Fixed an infinite loop in the clustering program when the sizes of cells are wildly different. In addition, we also prevent an infinite loop when there is no hope for further improvement. * Added a new pretty print of the annealing table which shows more data fields. The on the fly table is still available but much smaller. * Fixed problem with spareinst code in the placer which cause a crash when the spare logic placement was performed. * Fixed problems with a crash with small vertical rows. Was an internal initialization problem. * Added new global spare algorithm. This algorithm does a much better job of spreading cells uniformly over the core area. * Now we properly measure all multitier defined cells. Updated the Tcl function measure_double_height_cells to acomplish this function. * Now the translator can draw spare instances. Also, added ability to draw gravity members for both placer and translator. Was unimplemented. * Updated syntax so now it can take multiple copies of -e on the command line. Each -e raises the check level. * Updated the license info command so that it uses a formatted table so that the output is clean. In addition, added the working directory field. * Added ability for the iceditobj code to selectively draw colors which haven't defined as layers. Added the iceditobj draw and colors commands. psi : Jan 28, 2015 * Added ability to run extract datapath Tcl code multiple times. * Fixed problems with using global signals as tieoff cells. This is problematic in general and may result in the wrong spare cells being extracted. Now you will need to explicitly furnish the new -use_globals option to force the behavior. * Fixed problems with extracting prerouting code. Now code does not throw away non-routing layers as a side effect. * Added more messages to the extract prerouting process to let the user know what is going on. * Fixed problem with the spare gravity code to the algorithm that was added in chi. Code was looking at wrong instances to determine gravity. * Added ability to ignore multiple bindings to an instance when adding Tcl bindings. chi : Jan 5, 2015 * Improvements to handle net weighting in the cons_options.tcl file * More improvements to multi-tier standard cell placement. * Now we prevent a crash when multitier standard cell is placed erroneously in a top row where part of it would no longer be in the core. * Now the Tcl Disjoint Set operation returns an error message when it cannot find the element of the set during a find operation. * Now we only report verilog missing cell errors for cells that are actually referenced and not missing cells below any cell with actual layout. * In the translator, make sure that we properly handle open graphics connections especially if they have been withdrawn. * In the floorplanner, we only make connected instances active for cell movement. Speeds process greatly when invalid designs are floorplanned. * Added code to properly remove the overlap for multiple row high standard cells. * Updated cell positioning code to handle multi-row high standard cells. * Added the -net and -netindex option to the icinstance pin command. * Updated spare cell extraction code so that gravity is only assigned if the spare cells are in a module with connected netlist objects. * Updated the load_check code to handle instance based table format. phi : Nov 23, 2014 * Now the placer does not exit when clustering information is in error in the hierarchical placement mode. Now placer tries to do the best it can. * Fixed a problem with the placer when rigidly fixed neighborhoods are present. * Added the |tcl option to the icmessage routine so now the message can be returned to the Tcl interpreter. * Added the ability to surpress confusing warning message when processing fixed constrains using the Tcl command icfix_inst get. * Fixed a major gridding problem when rigidly placed neighborhood constraints were present. * Added the missing Tcl function iccluster delete function. * Fixed a problem with the translator converting fixed constraints to the placer's form. Now we keep it in the form the user gave. * Now icalert -graphics messages will properly deiconify and push message to the front of the windows. * Added the ability to detect conflicts with rigid neighborhood constraints and clusters. Now shows any clustering errors in a graphics popup. upsilon : Nov 14, 2014 * Added tests to the placer initialization routine so that double height rigidly placed cells are correctly placed. * Fixed a crash when double height cells are in the wrong row. Now program will not crash even if the double height cells are in the wrong row. * Fixed a problem when a cluster is so improperly defined that not a single cell is correct. The entire cluster is ignored now. * Fixed a problem with all the spares being in a single row. This was actually due to the fact that the spares were specified with gravity but there were no member cells in that gravity domain. Now we just release the cells to the generalized spare columns so we can get a good placement. * Added better error messages for overlapping pads. Now we shown the coordinates of the overlapping pads. tau : Nov 10, 2014 * Fixed problem with row definitions not being updated in hierarchical mode in the placer. This was causing placer to stall in hierarchical mode. * Added -signal and -instid options to the icnet binding command for completeness. * Fixed problems with icfix_inst keepout command. It now works properly. * More support for neighborhood keepout constraints. sigma : Oct 8, 2014 * Added the numpins field to draw nets widget so user can see the number of pins on a net. * Improved the datapath extraction algorithm so that it can properly extract a one stage datapath. * Fixed problem with the pin optimization algorithm crashing in the general floorplanner. * Added NEIGHBORHOOD KEEPOUT construct as a convenience. This is the logical inverse of a neighborhood. * Reimplemented the SOFTGROUP constraint so it is much more effective. This constraint now also has the PERMUTE and NOPERMUTE property. rho : Sep 24, 2014 * Improved an error message when rectilinear cells are not more than one row high. * Now standard cells as hard cells are no longer incorrectly treated as spare cells. This was causing these cells to shift randomly. * Added ability to save and coordinate all random seeds to the placement program. Now the program creates a seed file. * Now all programs take -R as a standard command line argument. * Added better error messages to missing modules during Verilog translation. * Now we properly expand the row pedestals when extracting placement blockages. Previously, it was only looking at the pedestal line during translation. * Fixed typo in error message for driving pin path calculation. pi : Aug 27, 2014 * Updated the load_check code so that it does not report false errors due to compacted switches and tie off cells. * Added the Tcl function ::icnets::is_tied_off for use in load checking function. * Added the ability to modify the pin type of a model pin in the translator. * Added the icdatapath threshold command so that the identification of datapaths is more controlable and more realistic. Perfect nets now have a higher threshold but it is user programmable. omicron : Aug 17, 2014 * Now the hierarchical placement algorithm properly handles users defined cluster and has the ability to show them in the placement algorithm. * Updated the hierarchical placement algorithm to handle vertical path constraints properly. * Fixed problem with hierarchical placement algorithm with user defined clusters not obeying legal block class constraints. * Added wire length monitoring tool the standard cell placer. * Added the ICSC*graphics_wait : final command to the .par file so we can stop at the last iteration of the hierarchical placement algorithm. * Added better error message when pedestals overlap in the floorplanning tools. * Fixed problem with incorrect reporting of an overlapped pedestal definition. * Fixed problem with the placer stopping due to a perceived immediate FPE error. Internal calculation was incorrect. xi : Aug 12, 2014 * Now we support an implicit or default supply cluster, that is, all cells not in the specified supply clusters are put in a default supply cluster. This is done automatically as a convenience. * Fixed problem with hierarchical placement which was causing two failure modes. In one case, it cause an abort and the other case it caused one row to have an extremely long length. This occurred when neighborhood constraints were present but not properly processed by the placer. * Fixed problems with the row generation code failing when double height cells and mask operations are requested in the .con file. * Added new experimental datapath placement algorithm which searches for perfect nets to align the datapaths. * Fixed problem with datapath calculations when the folding number of rows is zero. * Added more information to the datapath graphical user interface. Now it shows the quality of the datapath which has been added as a constraint. * Now prevent a crash when spare data is in error. Placer would crash if an instance was specified twice, once with gravity and one without. * Added the -net option to the icinstance bindings command so we can filter for a net connected to a given instance. nu : July 24, 2014 * Added error checking to icread_verilog translator command so that incorrectly translated netlists do not go unnoticed. mu : July 21, 2014 * Added ability to measure multiple row standard cells automatically if they have been marked as double height cells. * Now alert boxes are searchable text windows. The iclogfile::readfile command now has a search mechanism for looking at the log file conveniently. * Added missing Tcl command "icmodel used" to query whether model has been used. * Added missing Tcl command "icrow height" to obtain the row height. * Fixed problem with translator terminating prematurely when a data error occurs during netlist flattening. Now if a graphics report is requested, the error is displayed properly instead of the program terminating. * Added autocenter control in the placer. * Fixed problem with exhaustive placement optimization being turned off. * Added the -index option to the Tcl icinstance bind command for completeness. * Added the -signal option to the icmodel pinnames Tcl command. * Added the icmodel pincopy command to allow easy manipulation and addition of pins based on current pins. lambda2 : July 17, 2014 * Fixed crash in global routers due to rectlinear standard cells. lambda : July 17, 2014 * Added multiheight row cell support to the floorplanner and syntax checker. * Now we don't allow large multiheight row spare cells. Very large things should be placed normally and not be spare cells. Double height cells are ok but 3 or more rows doesn't make sense currently. * Global routers do no draw the sizing layer information by default so that the run doesn't slow dramatically in graphics mode. * Fixed problems with double height cell overlap in the global routers. kappa : July 9, 2014 * Added more support for multiple height cells (> 2 rows). Added the MULTI_HEIGHT keyword to the constraint file so these MULTI_HEIGHT rows can be defined. * Fixed problem with extreme memory use when prerouting is present. Placer was allocating gigabytes of memory instead of a few megabytes. * Added the -Q option to ICTk and ICtclsh programs to quiet the output. Also added the -A option so the user can control whether the invoked program sees all of the arguments including itools control options or just the Tcl arguments. * Now prevent a crash when a multiheight cell are in the wrong row. * Now handle multiple height spare cells. iota : June 18, 2014 * Fixed problem with placer surpressing outputting error messages when detecting overlaps. The large number of warnings swamped the error message. Now all overlap errors are output. theta : June 17, 2014 * Fixed problems with processing rigid neighborhoods in the placer. Previously, neighbors could be overlapped among themselves. * Fixed a crash in the global routers when split or complex rows are present. eta : June 11, 2014 * Fixed problem with initial placement of global spare cells in the placer. * Improved the performance of the hierarchical cluster algorithm when supply clusters are present. The number of degrees of freedom was increased resulting in a better final wirelength. zeta : June 10, 2014 * Now we do not corrupt properly assigned block classes when running placement in hierarchical mode. epsilon : June 9, 2014 * Added the icrow super command to manipulate super rows. * Now power supply constraints are handled properly when supplied by the user with mask constraints. * Now spare logic cells without gravity are properly added when complex rows are present. * Updated placer to understand cell instances with both neighborhood and block class constraints. Now graphics properly displays such cells. delta : May 27, 2014 * Now the itools.con row constraints are automatically updated so that any SUPPLY specified will automatically get a unique class. * Began work on improving the mask capabilities related to row definitions in the constraint file. * Now for completeness, we allow an instance to have both a fixed constraint such as a neighborhood and an initially fixed place. * Added the icrow class and icrow supply Tcl commands to the icrow command. * Added ability to draw and hide spare instance cells in the placer. gamma : May 14, 2014 * Fixed problem with crash in placer when supply clusters are assigned with too many rows. * Added icinstance checkclass in the placer. beta : May 8, 2014 * Updated the icpath:write_report Tcl script to avoid nets with no defined drivers. * Added the isearly subcommand to the icstage in the placer. * Added ability to view all instances of a given prefix (of the instance name) so one can view the logical hierarchy of the netlist in the placer. * Added the ICSC*eco_autodetect option to find differences in the netlist and the .pl1_in file automatically. While this eliminates the ability to check for errors, it makes ECO specification much more convenient. * Fixed a crash in ECO mode when cells are added without mentioning them in the constraint file. The eco_autodetect feature also prevents such a crash. * Now .pth file reports how many constraints of each type are present. * Added a report to the supply clustering algorithm so the user knows which rows have been assigned. * Improved and corrected the behavior of power supply clusters. Added the MONITOR keyword to cluster constraints in order to monitor the constraint. * Improvements to the Verilog translator. Still more work to be completed. * Fixed crash in itools placer when spare instances are present. * Added -netidx option to the icinstance binding command. * Added better error messages to the Verilog translator. Now include probable line numbers. * Added ability to read and understand Verilog parameters and access them using the icmodel paramater command in the translator. * Fixed translator so that it reads Verilog defparameters properly when entered as a comma separated list. * Added thec iccost spinelimit command to the detail router to limit excursions of the spine when trunk routing. * Added the TIEOFF model atttribute. * Added the translator command icmodel attribute, hasattribute and parameter subcommands. * Added the model attribute TIEOFF to model tieoff cells. alpha : Mar 25, 2014 * Sif translator now takes system grid into account for proper scaling of vias. * The second generation global router now has a working sizer layers control. * The second generation global router now ability to ignore pins on wrong layers. z : Mar 25, 2014 * Added the ability to detect and place spare cells that are in the netlist and unconnected. Spare instances at the top level are placed in columns. Those placed within the Verilog hierarchy will be placed relative to the cluster of cells comprising of that module. This is a type of gravity to the central mass of a cluster. * Added the sif to itools translation of vias. y : Mar 8, 2014 * Updated Verilog translator so it recognizes I/O ports which are power and ground. * Improvements to the license server so it can report statistics better including the generation of a .csv file. * Initial implementation of spare instances. Still needs work. x : Dec 23, 2013 * Now allow pins in the global router to occur on NWELL and PWELL layers. w : Nov 19, 2013 * Fixed problem with keepouts being assigned the wrong layer in the sizer during global routing. * Added the icsizer eval and icsizer numobjects commands in the global router for completeness. v : Nov 8, 2013 * Fixed crash in the global router when freeway assignment is requested and a global signal is ignored for routing. * Added more debug capabilities (-debugmodel switch) to the plugtie Tcl code. u : Sep 18, 2013 * Fixed problem in placer not obeying cost_only keyword. It was doing orientation optimization when it shouldn't. * Fixed problems with icoutput command in the placer when filename was specified. t : Aug 17, 2013 * Fixed problems with missing ictools_version command in the global router. s : Aug 16, 2013 * Fixed problem with cost_only not working for hierarchical mode placements. Now the placer calls flat mode for cost_only as it should. r : Aug 7, 2013 * Added the icmodel rows command so you can find the number of rows of a given core cell. * Now we keep graphically displaying all of the members of a cluster as the placement evolves so we can give better info to the user. In addition, we now allow user to specify "members <# | name>" as a shortcut to input the desired cluster. * Fixed plugtie code in global router and added a plugtie report file which tells user why plugtie was added. * Added control of graphics display of sizer layers in global router. q : Aug 7, 2013 * Fixed a problem in the global router when non-standard cells move such as ports or 3 dimensional objects during placement improvement stage. Previously, staple segments were not being updated properly. * Changed the global net output routine so that if the user doesn't create any pins but just defines a global name a warning is issued and not an error. * Added initial new Synopsys parsing algorithm. It is not complete at this time. p : May 23, 2013 * Added program timeout to the standard cell placer and the two floorplanners, ifp and ipg. The timeout can be added to the .par file using the keyword *timeout and can be given in seconds or of the form #h#m#s such as 1h2m3s - 1 hour 2 minutes and 3 seconds. * Revamped the output display of the generalized placer/floorplanner igp so that it is easier to read. o : Mar 8, 2013 * Added the ability to view fixed cells and hide them in the generalized floorplanner. * Added a system call to the backup directory Tcl to help with balky file systems. * Fixed a problem with the translator complaining "This function called on the wrong type of database." * Fixed problems with generalized placer/floorplanner going into a infinite loop when in pin optimization mode is enabled and no pins are available for optimization. n : Mar 8, 2013 * Fixed an infinite loop in the placer when multiple row cells are present. * Added initial support for directly using a SDC file to control timing driven placement. Currently, only the stubs are implemented. m : Feb 29, 2013 * Added icsizer eval and icsizer deck commands. * Added ability for the translator to relocate the position of the log file. * Added autodetect script to detail router which was missing. * Now the detail router properly handles hierarchical instance placements properly. * Added the -detect_io option to the icread_verilog command so we can automatically set the explicit power and ground ports flag. * Fixed a crash with multi-row height cells. This will allow a future version to place multi-row height cells to be placed arbitrarily. * Added internal support for polygon figure processing for more efficient processing of abstractions. * Added icinstance renumber TCL command for completeness. * Now the iclayers routing command takes an additional optional argument called -include_nonmetal to include nonmetal routing layers such as poly and diffusion. * Now the ictools_version and icversion command has two new subcommands: major and minor to return the major and minor version numbers. l : Oct 25, 2012 * Improve EZ so that I/O layers of pads/ports may be chosen by user. * Improved the ability of the detail router to compact channels using expansion. Now the virtual channels expand properly. * Made changes so that constraints are less context sensitive. Previously, the keyword PAD tripped up the constraint generator into a false syntax error. * Added the -primary option to the icgeometry layers command and added the icgeometry instance command for ease of use. * Added the icfix_inst exists and icfix_inst init commands so we can properly initialize fixed instances and know if an instance has a fixed constraint. * Added iclayers equiv, iclayers equal, and iclayers purpose Tcl routines for generality. * Added the -primary option to icmodel layers command to allow the return of just the primary layers that exist in a cell. k : Jul 11, 2012 * Fixed translator so the icexit returns the proper exit code to the operating system. * More improvements to handle arbitrary high standard cells. * Fixed crash in global router due to new code. j : Jun 27, 2012 * Fixed more problems introduced to handle arbitrary high standard cells. i : Jun 25, 2012 * Fixed problems with crash of single height standard cell when fixed in the row. This problem was introduced starting in version 43f. * Added support for arbitrary strings in Verilog defparam construct. Strictly, speaking this is not in the Verilog spec but it is useful. h : Jun 13, 2012 * Fixed problems with global routing crashing during cell swap initialization. This bug was injected when we added the rectilinear standard cell capability. * Fixed problem with unlap removal which was yielding a different answer than previous version of the placer. * Added support for naming sites so we can handle multiple row high cells. g : Jun 1, 2012 * Improved the rectilinear processing by rewriting the basic move code for multiple row height cells. Eventually, the placer will be able to move these large cells between rows. * Added the ability for the user to constrain the length of a given row overriding the row geomtry definition. This is accomplished by the use of the LEN_FIXED attribute to a row. Previously, the row length was fixed to the row geometry the user provided. Now an optional number following the LEN_FIXED attribute allows the row length to be calculated from the given number. This is just a convenience attribute to allow easier experimentation with the row topology as the program now will calculate the geometry for you. * Fixed problem with crash when processing I/O nets during parsing. f : May 23, 2012 * Added RECTILINEAR attribute to standard cell models so that we can properly process groups of fixed standard cells which have irregular boundaries. * Added preliminary support for Open Access databases. This version opens the database but does not yet understand all of the tables. e : Apr 4, 2012 * Added side pin access support to the placer. Now the final global routing will be much more controlled. d : Mar 14, 2012 * Added an algorithm to aggressively compact regions during detail routing. * Updated GDS2 writing code so that it outputs the angle properly. It was not generating wrong GDS2 just not standard. * Now we avoid remote checking of local hosts for host type. This is easy enough to do locally and so this removes unnecessary error messages when running on the local host. This applies to all parallel programs using the icdaemon. * Changed output of RELATIVE pad placement constraint so that it is consistent with the EXACT pad constraint. * Added a icdaemon startup button to EZ and added ability to control the region compaction algorithm. * Added scaling to ictools_pquad and ictools_quadtree Tcl packages for convenience and completeness. c : Feb 8, 2012 * Now the detail router checks pad placement when in exact mode to make sure that the pads are not overlapping. This can be overwritten by pad constraints in the constraint file. * EZ now generates a better entire.ddo script for notch filling. Not perfect yet but better. b : Feb 1, 2012 * Added icpath hweight and icpath vweight commands for completeness and control. * Added the -position switch to the icnet pins command so we can easily find the (x,y) positions of pins. This was added as a convenience function for the user. * Added the icpath command to the translator so we can calculate path information and make reports. * Added the -init option to allow calling icpath::write_report from the translator. Also added the -test option so we can output all paths. Added another set of fields to describe the furthest sink from the driver. a : Jan 12, 2012 * Add OFFSET feature to datapath constraints so one can control the rows where the datapath is added. Version 2.0.0 pre42 - released Dec 29, 2011 Reissued Jan 3, 2012 * Fixed problem with translator not assigning correct pad side. ======================================================================== gamma : Dec 16, 2011 * Added more error checking of ill specified clusters. beta : Dec 7, 2011 * Added the icmodel PERMUTE type so we can recognize permutable cluster models in the placer and floorplanner. * Updated output routine in itools translator so that it will automatically determine the pad side if none is supplied. This used to create an error on output. * Fixed problems with PERMUTE clustering when cluster is split among rows. * Added better error message when a cluster has specification errors in it. alpha : Nov 23, 2011 * Now prevent a crash in the placer when no nets are present. * Now try to determine pad side when writing .pl1 files. Was causing annoying errors unnecessarily. z : Nov 17, 2011 reissued Nov 21 * Now we check to make sure I/O port is on valid routing layer. * We make sure I/O port is unique by appending _TW to the name if the name of the port classes with the design name. * Fixed crash in cluster code when names are not unique * Updated report for showing path timing constraints * Fixed notch filter code so that it does not disconnect nets when in the netlist is not contracted. * Fixed DRC errors related to notch filling aka intraspacing errors. * Added icnet bbox command and ability to write a report based on path LENGTH constraints. y : Oct 31, 2011 * Now global router supports split clusters properly. x : Oct 26, 2011 * Fixed problem with splitting clusters more than 2 times. The order of the clusters was in error. * Updated translator to handle ROWS constraints for clusters. w : Oct 19, 2011 (reissued Oct 21, 2011) * More improvements to the split clustering algorithm. Now we take high aspect ratios into account and the ROWS keyword is used to limit the maximum number of rows of a cluster. Added the members options when drawing clusters in the placer so we can see the constituents of a split cluster. * Fixed crash due to missing initialization when split clusters are present. v : Oct 14, 2011 * Improvements to the split clustering algorithm. Previously, the algorithm had the wrong logic with respect to permute attributes. u : Oct 12, 2011 * Now we properly adjust the positions of the sub clusters and make sure we don't fix cells too early during placing. This was visible using graphics under the hierarchy control. * Now properly list the clusters in the placement program. Previously, was listing all cells. * Improved the icnets::netlist_check Tcl procedure so that it calculates percentage of cells interconnected properly and added improved error messages. t : Sep 30, 2011 * Fixed problems with outputting prerouting. Bug output fixed and nonfixed prerouting together twice in the constraint file. * Added icnets::netlist_check so we can alert users to defective netlist, ie. ones that have no interconnections. * Added the -no_routing, -fixed_routing, and -unfixed_routing options to the icread_ic command so we can suppress the reading of previous routing. This was causing a problem in translation when unfixed prerouting exists. s : Sep 30, 2011 * Fixed alignment problems with double height cells when port optimization is enabled. * Now properly adapt row placement when double height cells are present and row adaption is enabled. * Added support for fixed net prerouting extraction based on geometry size. r : Sep 26, 2011 * Addded the fixed_nets option to the preroute extraction Tcl translation command. * Added proper scaling for output of prerouting cell boundary. * Now properly output split clusters instead of crashing in iplacesc.v1. * Fixed problems with misaligned cell output when rows contain a hardcell. * Added cluster_split_weight option for controlling movement of clusters. q : Sep 6, 2011 * Improved error messages in second generation global router. Fixed memory access violation in global router when freeways are present. * Updated prerouting translation code to match new Tcl formatting. * Added icplacepads::read_io_placement as a way of updating I/O placements. * Now properly set the pin type in the global router for prerouting pins. * Added the icgds trace command so we can label GDS2 databases for prerouting. * Fixed problem with initial configure of cells being wrong for double height cells in the placer. * Added ability of placer to handle multirow clustering. The non-permute version works in this version. p : Aug 23, 2011 * Added ability to label GDS2 using bounding box of structure and an instance label. This is useful for ECO mode. * Added the -include_placement_mcrs on a icgeometry gds build so we can manipulate mcr data of placements (both AREF and SREFs). In addition, we added the -mcrs option to the icgeometry enuemrate command to be backwards compatible. * Now support the ability to have comments in continuation cards of a SPICE deck. * Prevent a crash during translation when sizer routine encounters a layer it hasn't seen before. * Added ability to detect frozen states in igp similar to iplacesc. Added tracking of time since last improvement in cost. This greatly speeds the execution time when running only pin optimization. q : July 15, 2011 * Rewrote lef parser so that we properly add pin attributes. p : July 15, 2011 * Added updated load check commands. * Added icstring::remove_whitespace Tcl function. * Added icmodel pinfunction command. * Added expr = expr rule to pin function so we can support switch logic. * Now we make sure that the row centers are rounded to the epsilon grid to avoid roundoff errors. * Fixed roundoff problems with calculating core size. o : Apr 13, 2011 * Added load_check comands. Added icinstance type command for convenience. n : Mar 18, 2011 * Fixed problems with compactor taking large amounts of runtime. * Now placer tells which layers it has detected for port compaction. * Fixed problems with compactor not using the correct port layers for compaction. m : Mar 16, 2011 * Fixed problems with double height cells and clustering placement mode. Previously, double height cells were not accounted for properly and row alignnment suffered greatly. l : Mar 9, 2011 * Fixed problems with not adding Cadence placement characters to the pcmap file. * Fixed problem with icconstraints::convert_cover_to_pad_pins itranslate Tcl code so that it now properly handles LAYER 0 softpins. * Fixed problem with to exit itranslate when window is destroyed by window manager. Now program exits when window closes. * Fixed problem in global router where side access pins were not accounted for in pad placement code result in bad region definitions. This prevented the global router from making a good tile graph and the result was a "missing anchor" error during the routing of I/O pins. k : Jan 28, 2011 * Fixed problem with pin optimization due to translator problem in Verilog translator code. i : Jan 18, 2011 * Fixed problem with global router complaining when cover ports are in error. Now it is a warning if a valid port exists. * Reverted to old scaling mechanism for time being. * Now prerouting doesn't call notchfilling as it makes it more complicated in the end. h : Jan 4, 2011 * Fixed problem with timing constraints as they didn't pass regression test as a roundoff error was introduced into pre42e. Now regression test passes. g : Jan 3, 2011 * Fixed memory leaks in global routers. f : Dec 27, 2010 * Now we make sure to ignore logical pins during routing. * Now prevent a crash in the placer when just two cells are placed and design rules are strange (larger than the cells). * Added support for file mode and header and trailer control for the icwrite_lef command in the translator. * Added icnets::io_net Tcl command so one can determine if a net is an I/O connected net. * Added the -all switch to the icinstance pin command so we can list unconnected pins. * Added MINSTEP and FREQUENCY unit rules to LEF translator. * Applied patch to Tk so that MouseWheel events work properly when the MouseWheel is not present. * Fixed problems with synopsys .lib reader. Now we support two variants of quoted index strings. In addition, when the translator does not complain incorrectly when a feedthru is present. * When there are no moveable cells in a design, the placer now uses the feedthru cell as the average width of a cell in gate array mode. * Added iccolor::color_gradients Tcl command so we can make nice color gradients for showing congestion in the global router. * Now show routing when calling routing view in EZ. e : Nov 2, 2010 * Added the net_vertical_path_len and net_horizontal_path_len Tcl procedures to the translator for convenience. * Fixed a major problem calculating wire length of nets which have more than 6 pins in the placer and floorplanner. * Fixed problems with parsing netnames which conflict with keywords in the constraint file. Now any string is supported as a net name. * Added support for vertical and horizontal length constraints. In addition, we added the weight option to the constraints. * Added the icnet weight Tcl command to modify net weights. * Added icmodel hardcell command. * Added ability of translator to calculate wire length using the icwirelength Tcl command. * Now DEF translator can handle standard cells which have been fixed as hardcells. Needed for ISPD benchmarks. Fixed translator so the EDITCCELL properly displays the highlighted cell. d : Sep 4, 2010 * Fixed problems with translating DEF row definitions. c : Aug 30, 2010 * Fixed bug in track layer list syntax. Now DEF design string is an arbitrary string. * Now the global router does not create an error when side pins are present. * Now global routers properly handle user ignored pins. * Now properly make feedthru cells when purpose pairs are present. * Fixed problem with contour detail router. It was not tracing nets properly. * Fixed problems with new net display code. Now account for title row and so all nets are now visible. Previously, last net was not visible. Fixed problems with port placement algorithm. Previously algorithm was not traversing entire hierarchy to discover obstacles. b : Apr 23, 2010 * Fixed initialization problem with clustering cells in the placer and floorplanner. * Now we properly handle transparent covers in the second generation floorplanner. * Added timeout option to prerouting. In addition, we added a feature to extract an abstraction from a routed subchip called icabstract::design. * Added the Beautify Nets with Errors command to the detail router in order to get a better completion rate. * Added the Check Area Rules command to the translator to check vias when in the via context. * Added and updated EZ documentation related to the chosen_iteration option within the global routers. Now we support a new option called min_width which picks the global routing configuration which has the minimum width. * Added the icconstraints::extract_placement_blockages Tcl translator command so we can automatically create placement blockages. * Fixed problem with iroute dropping geometries which lead to design rule errors. * Added the libitools_tktable module for building better and smaller memory footprint tables. * Fixed problems with reading long GDS2 strings. Wrong limit of 44 was changed to proper limit of 512 characters for a GDS2 string. * Added the icinstance isa_io type command for convenience. Added the -notcl and -tcl option to the icnet name, icmodel name, and icinstance name commands so one can output strings as needed. * Added the icnet dindex command so we can use the new Tktable facility to chose redrawing of nets. Uses substantially less memory than previous implementation of the draw net GUI. a : Mar 1, 2010 * Major rewrite of the data structures in order to support vias properly. Prerouted vias were problematic during routing output because they were not represented properly which necessitated major changes. Via are now properly represented in the .lib file. * Added the itools_remote package to implement the icdaemon test command which allows us to test whether the parallel daemons are working properly. * Update the track constraint definition to reference layer by name instead of only its layer number. * Fixed problem with error message when icdaemon does not work. Now the host and port reference the current connection. * Fixed crash due to clustering and neighborhood constraints. * Added the icrule minarea command in order to turn off minarea checking when prerouting to the detail router. * Added the iccompact_channel expand command to the detail router in order to expand spacing between channels. Also added the icrestore -pads command to rebuild only the pad instances. Version 2.0.0 pre41 ======================================================================== * Freeze : March 1, 2010 zeta : February 21, 2010 * Fixed highlight of group in the placer. * Added orientation optimization to the NOPERMUTE cluster type. This is accomplished by adding ORIENT -1 to the instances of the cell which need optimization. Currently, hierarchical optimization is not implemented. * Added the icnet mst command so one can display the MST of any net. * Fixed problems with the icpad relative and icpad exact commands. Due to a mistake in processing the arguments, these commands previously did not work. * Now the clocktree synthesis code supports SPICE .lib statements. In addition, we now prevent an infinite loop when building data lookup tables. * Added the icdaemon -test command so we can test remote daemons easily. * Updated icread_itools::state command so that it supports versioning and reads the constraint file in the same manner as the analogous program. * Fixed problem with icdatapath::getDPBusIndex which had an extra level of braces and caused trouble in evaluation of bus index. * Improved the clocktree report so that a report can be generated post global routing as an early indicator of problems. Added support for SPICE libraries. * Added the icdatapath stagesize and liststage commands so we could implement the stage info option in the datapath display gui. * Added more complete filtering and building constraints. Added icmodel mergecover and the icnet parasitics -exists Tcl command to the translator. * Upgraded to ngspice version 20. * Fixed problems with not detecting cover cells properly when placing ports. * Fixed problem with failing to update a hierarchical cluster properly. * Now we output multiple lines of an imported DRC results file. * Added the iccluster exists Tcl function. epsilon : Jan 9, 2010 * Fixed problem with removing pins properly when they are translated into prerouting. * Fixed problem with drawing hierarchical netlists. * Added the icmodel isa_io command to detect itools port/IO models. * Now prevent crashes when setup/hold constraint are asymmetrical such as reset constraints. * Added the -nocover option to icwrite_gds2 so we can avoid writing cover cells. * Fixed problems with reading antenna constraints when in a separate LEF file. * Added comprehensive logging to the license server so one can monitor license usage. By default, this is enabled and all license transactions are now logged to the ~/.itools/iclicensed.stat file. * Added new design constraint to detect when poly routing is not isolated. * Now SPEF reader properly processes the passive component unit values. * Improved the hierarchical pin placer. The rewrite is almost complete. delta : Dec 31, 2009 * Fixed problem with splitting clusters in rows. Now the default is that the cluster must be larger than 1.5 x length of row. However, we have added a new parameter called cluster_split_param which allows the user to modify this default. gamma : Dec 29, 2009 * Fixed problem with crash of clusters when timing constraints are present. beta: Dec 18, 2009 * Fixed problem with 3d placer when core definition is bogus. Previously, the placer crashed - now we just report an error and continue as much as possible. * Fixed problems with clustering gaps and crash in placer. * Fixed problems with vertical row clusters. * Added hierarchical drawing support for design context in translator. * Now prevent a crash in the global router when pins do not have layer information. * Initial code for detecting isolated poly gates, that is, poly routing that does not escape to the first metal. alpha: Dec 10, 2009 * Added the iccluster add/remove commands to manipulate clusters during translation. * Added the res_sum and cap_sum options to the icparasitics trace command. * Major improvement in cluster processing especially PERMUTABLE clusters. * Added the -connected option to Tcl command icinstance bindings for convenience. * Added Hierarchy control to the row-based placer for debugging purposes. * Now we make sure that cluster member instances exists and that the clusters member instances are row-based cells during translation. * Fixed problems with reading SPEF files and dumping their contents to a SPICE netlist. z: Nov 24, 2009 * Fixed crash in detail router when via definitions are suspect. Crash occurred during trace of a route with bad via definition. Also modified so via definitions can contain via cut boundaries. * Added ability to draw connected pins in the translate program. This allows us to select by net and helps in debugging data. * Fixed crash in hierarchical pin optimization when prerouting is present. * Added the -discover option to the icmesh detailed routing code so the detail router can discover the power and ground mesh network that the global router instantiates. * Now the icgeometry intersect command can take an empty area list which :epresents searching the entire chip area. This was done to make writing script easier in the detailed router. * Added missing icreport_errors wire_extension command to the detail router. * Added the icstring::strip_suffix Tcl command for utility and completeness. * Added the icdraw cover command so we can draw cover cell data on top of model cell data. This is very useful in debugging library models. * Added the icparasitics layer command so we can properly draw a .spef file. * Fixed problems reading clk_width in Synopsys Liberty parser. * Now we properly set the power/ground pin type attribute for power and ground prerouting. * Tcl print tables have been updated so that floating point precision is adjustable. y: Nov 17, 2009 * Further improved the result of the hierarchical pin placing algorithm. Now it does a reasonable job even in the face of bogus data. x: Nov 13, 2009 * Rewrote the igp floorplanner graphics so that one can see the freeways drawn properly. * Improved behaviour of hierarchical pin placing algorithm. Previously, the lowest cost state was not preserved. w: Nov 7, 2009 * Added ability to rotate vias in Tcl command icvias::convert_lib_via. * Now prevent a crash in the detail router when data is bogus and vias are not properly defined. * Added the -flatten and -offset options to icmodel keepouts. * Now relaxing vias is turned off by default now. This was causing design rule errors. * Now we don't complain in the global router if pins are on diffusion layer. * Added the icgeometry transform command so we can rotate vias in the translator. * Improved message output routines so that we can suppress errors messages when desired. Now program end tells number of suppressed messages. * Added message options to the Tcl command icmessage. This allows us to suppress messages if desired. v.2: Oct 31, 2009 * Fixed problems with Synopsys library output problems into the itools library. Previously, empty tables were being output creating syntax errors during prerouting. This was due to scalar tables. * Improved the parameter file Boolean operations to handle any of the Tcl variants: yes, no, on, off, true, false, 0, or 1. * Added | to TWplug instance name to make it compatible with Cadence. * Added the icmodel wires -flatten -new_port command so we can detect ports from wires and net connectivity geometries present in the library model. * Fixed igrouter so that it doesn't output an error message when no rows are present. Fixed problems with not finding maze routing target. * Fixed problems with row-based placer crashing when placing double height cells in ECO mode. * Now floorplanners properly connect implicit nets. * Now we convert any large pin geometries in the top level cover cell into prerouting automatically. * Fixed problems with not copying all pieces of a required cell's hierarchy. * Added the -half_height, -single_height, and -double_height option to the icrow options command. * Added the -nopads and -nosides options to the icwrite_ic command. * Fixed iclayers command so that it works properly for iclayers layer_index commands. Previously, it only worked properly for iclayers layerName commands. * Added the -ignore option to the icmodel pins command for convenience. * Added the ability to display a model in all of its possible orientations when in the draw model context in the translator in graphical mode. * Updated the ::icconstraints::convert_cover_to_pad command so that a -ignore list and -delete_ignored options allow one to delete pads in the case where the data should be treated as prerouting. The routine convert_cover_to_prerouting now uses the new icmodel wires command. u: Oct 20, 2009 * Fixed problems with igrouter and zero width switchboxes. In addition, switchbox generation is now off by default for now. * Improved hierarchical pin placement capability. Previously, ports were not initialized properly. * Improved row-based ECO capability when in fix die mode. * Fixed problem with drawing nets in MST mode when hierarchy is present in the design. * Added iclayers primary help command and added the iclayer primary equiv Tcl command to list equivalent purpose pairs. * Added the icmodel wires command to extract prerouting from wires present in the covercell. * Fixed problems with bus pins. Previously, the translator reported an error in hierarchical binding when no such error existed. * Added snap to grid option to the edit cell GUI. * Added the -abs_fixed_cons switch to the DEF reader so that we can handle multiple height cells properly. t: Oct 16, 2009 * Fixed problems with error message in igp when floorplanning hierarchical netlists. * Updated Synopsys liberty parser to handle new options. * Improved handling of row blockages - not complete. s: Oct 14, 2009 * Fixed problems in hierarchical placement engine and reworked the bus naming and processing infrastructure. r: Oct 13, 2009 Improperly built and removed. q : Oct 9, 2009 * Added the iclayers primary command so we can handle purpose pairs in Tcl scripts properly. * Fixed problem with ::icconstraints::copy_files command which did not properly handle lists with more than one item. * Updated ::icconstraints::convert_cover_to_pad_pins to handle cover cells with multiple ports even some not on routing layers. * Modified icvirtuoso::create_ios so that it now handles implied global net bindings properly. p : Oct 1, 2009 * Added icinstance source command and added the -tcl option to the functions icinstance model and icinstance name so these commands can generate Tcl escaped names. * Added source support to def and itools so physical cells can be tagged. * Added -pre_func option to the global router so use can perform initialization before global router iterations. * Fixed a crash in the global router during feed assignment when width constraint cannot be satisfied. * Fixed crash in iflow when it receives a wrong return value from a Tcl script. * Updated widthopt.tcl script to use correct global routing file pathnames. * Added icrow pedestal command for use in scripts. * Added DEF support for placement blockages. * Fixed a problem in the global router which caused a crash when a port was way out of the die region. * Fixed problems with layer directions and Tcl GUI. Was previously outputting all direction types when direction was unknown. In addition, we now properly modify the direction parameter when requested by user. * Added spacing table support to LEF parser. It has been supoorted in itools for quite some time but translation from LEF data was previously missing. * Added the icinterval Tcl loadable module to allow use of interval tree algorithms to Tcl. * Fixed problem with quoted string in the LEF translator. * Now we properly regard a bus pin as an equivalent pin when the the bus delimiter is changed from the default []. We currently only support one dimension arrays for library cell pin names. We do supoort up to 3 dimensional arrays for hierarchical netlists. * Now we build a default spacing rule when only a spacing table is given for a layer. o : Sep 16, 2009 * Fixed some problems with antenna routing. Some still remain. The final fix will be in the next rev. * Added sizer capability to the global routers. In addition, the global routers now allows the user to supply Tcl routines at the beginning, after placement, and at the end of each global routing iteration. * Major rewrite of the sizer algorithm. It now uses the new composite tile database so that in the future we can handle 45 degree geometries. In addition, the sizer code is now shared with the global routers. * Fixed problems with calculating the hierarchical placement of models. * Now perform transitive closure properly on library models so that placer correctly references all of the appropriate models. * Added the -cadence option to icread_verilog so that Cadence global signals are handled properly. * Detail router now has a speed improvement for pins with large fanout. * Fixed problem with iroute not being able to cross reference a region. n : Aug 1, 2009 * Now we make sure cluster instance names are unique so we don't crash placer. m : July 14, 2009 * Added support for automatic recognition of trunk routing within the detail router. * Added the ::icnets::class command to the detail router for convenience. * Updated the clocktree report so that the net information has the arrival times and maximum slew. * Added a common iclayers command to all programs for convenience and speed. * Updated Tcl translator code so that real I/O pins replace logical I/O pins added by Verilog reader. * Added ignore_io_layers to the global router so that side access pin feeds due to I/O may be modified. * Improved the translator's ability to convert 45 degree data into a rectilinear approximation. * Rewrote the icobject code in the detail router so we can handle just instance objects for searching. k : June 11, 2009 * Changed the global router error message "Not enough space to assign pins for model:" into a warning message. * Changed side_access and raw_need definitions so it is consistent with users understanding. * Now icnets::distribution can output pins with 0 pins which is usually power and ground. * Added the icnet get -filter option so we can sort thru the number of nets based on a regular expression. Fixed problem with pin flag in the icnet driver command. * Fixed problem with the icnet parasitics command in the translator. Previously, the net could be processed only once. * Added missing -foreign switch to icmodel keepout command. * Now we automatically call icsta exec command when the icsta trace command is executed so we don't crash the translator. * Added initial capability to extract and simulate a clocktree generated by itools. Began work on formatting report. * Modified global routers so that they can understand partially block IOs. j : June 5, 2009 * Added icnet driver Tcl command for utility. * Added the iccluster Tcl command to the translator so we can manipulate cluster constraints. * Added the -present and -build options to the icread_con command so we can selectively build constraint categories. * Added the icconstraints::update_clusters routine so we can update clusters so they have the proper orientation. * Fixed a problem with properly determining the number of inverter levels to add when building clocktrees. * Added the icnet buffer command so the user can add buffers to any net at will. The user can control fanout, buffer types, and depth of buffering. i : May 19, 2009 * Added support for Verilog compatible instance and net names when writing Spice netlist. In addition, we output comments for IOs when not in subcircuit output format. * Added support for VIA model types for convenience. * Added icvia exists command for completeness. * Prevent a crash when looking up spice model parameters. h : May 14, 2009 * Added preliminary layer:purpose pair support for layer definitions. * Fixed problem with via extent flag in the global router not being set when requested. * Now detect global signals in Verilog with ! at the the end by default and set their type to bidirectional. The user can still explicitly set the type but now we don't complain if a global signal's type is not set. g : May 5, 2009 * Began adding support for orientation initialization in CLUSTERING constraints. * Now logging function will log the version of the executing program for completeness and easier debugging. Improved the output .feed file produced by the global router and added the .feednets file which lists all nets with feedthrus. f : Apr 24, 2009 * Fixed a problem introduced in version 41b where clusters caused the placer to crash. * Rewrote the feed_search entry of the EZ global router html which is confusing to novices. Only this one entry was rewritten but the entire section needs to be redone so it is consistent. This will be done when the new options to the global router are completely finalized in this series. * Fixed problem with generated via rules in EZ. Generated via rules were assumed to always exist which is hardly the case. * Improved the display of diffnet via errors in the detail router. * Fixed typo on ICSC placement parameter: orientation_optimization. * Added orientation_optimization switch to the global router. e : Apr 21, 2009 * Now the placer traverses the clustering hierarchy of PERMUTE clusters during placement. * First cut at via extent algorithm in the global router. This is an attempt to accurately model 2 wide vias in the density calculation. * Added the -simple option to icmodel type command so we can return just the model type and not the model attributes. * Fixed the problem with the icnet properties command. Previously, all properties were erroneously being mapped to the DO_NOT_PLACE property. d : Apr 17, 2009 * Added LOGICAL model to the list of model attributes. This is similar to a LOGICAL pin but it applies to the entire model. Given this attribute the model is in the netlist but is not a physical entity. * Added the icnet clock Tcl command so we can define and list clocks conveniently. Previously, was only availabe using icsta in the translator. * Fixed problems with multiple bindings of signals for some complex cases. * Fixed problem with not writing PORT models to the floorplanner. * Fixed problem with complaint about complex ports when in a single row is global routed. c : Apr 10, 2009 * Now output side access debug data all of the time in the file groute/.feed. * Fixed problem with global router not using center pins and thereby not routing over the top of the cell when requested. * Fixed freeze in the placer at iteration 50 when only 2 clusters are present in the design. * Added the -nooffset and -foreign options to the icmodel pin command. * Added the -pintype option to the icmodel pinnames command. b : Apr 8, 2009 * Now the global router handle center ports over a confined channel over the row. In addition, we added the iccore, icpin, and igraphics routines to the global router for flexibility. * Added the measure option to the over_the_cell_capacity option to the global router parameters. In addition, we added the feed_fudge_factor option as a request so to overestimate the number of feeds. * Added the -namefilter option to the icmodel get command for convenience. * Now the icnet globalbind command returns the net type and supply voltage information if furnished. * Added the icmodel dummy command to allow the translator to inquire whether the cell has been generated as dummy model by the translator. a : Apr 7, 2009 * Added support for voltage supply constraints for global nets. * Added driver centering timing contraint for nets specifically clock nets. * Began work on relax_pin_access option for the global router. This will allow snaking of pins to the outside if room permits. Version 2.0.0 pre40 ======================================================================== Beta Release Mar 24, 2009 * Fixed problems with pin function definition strings. Now we always double quote the string. chi : Mar 18, 2009 * Improved installation script EZinstall.tcl. * Added -overlapping_ends_first option which replaces the erroneous -exclude_crossing_pins option. phi : Mar 10, 2009 * Now -implicit_globals is the default mode for binding Verilog positional pins. * Now the Verilog parser reorders the physical pins if a Verilog module definition is supplied. This behaviour can be turned off by using the -nomodel_redorer option to the icrread_verilog command. * Added the -sbox and -exclude_crossing_pins to facilitate clocktree routing. The -sbox or source bounding box option can also be used to increase the speed of power and ground routing. upsilon : Mar 6, 2009 * Added the -real option to icnet binding command so that we output just real pins and not pins created from fixed routing. * Updated parasitic code to handle fixed routing. * Fixed a memory leak in the placer when ports are placed in 3D. * Added -ignore_model_expr and -ignore_models options to the icread_verilog command so we can control which instances are added to the netlist. Also added the -implicit_globals option which tells the parser that power/ground global signals are not in the positional netlist. * Added the icexit_on_order_error to itranslate so that positional errors may or may not cause the problem to exit with an error. * Added debug to tell user when there is a conflict in the order between model definitions. If icexit_on_order_errr is set, we now exit the program. * Fixed an error in the Verilog translator when using a physical model. The pins in the physical model were being added in the reverse order. * First version to include NGSPICE. Integration is not complete. * Fixed problem in detail router where fixed prerouting was able to ripped up thereby defeating its purpose. Now we add prerouting even in the presence of design rule errors. Also began work on new notch filling algorithm. * Fixed problems in the row based placer with adding clusters to vertical rows. Previously, the cells were being added horizontally to vertical rows. * Added the ability to keep or throw away the initial bin packing placement in the placer with the use_initial_placement keyword. * Now limit the number of warning and error messages when outputting cells. We count the number of error messages but don't output them all but user can change the limit through the warn control system. See .wlog file for details. * Fixed problem in the translator with not generating any pins for the default feedthru when the user specifieds a layer but the layer is not a vertical/orthogonal layer. * Fixed orientation problem with side access feeds. Now properly add side access feeds when I/Os are present and need to be routed. tau : Mar 3, 2009 * Added the redundant_side_pin_feeds option to the global routers to control the removal of redundant feeds. Values may be off, max_explicit_feeds, or max_sidepin_feeds. * Now we always make sure to restore top level view of hierarchy at the end of the program. Previously, sometimes we were left in a lower level of the hierarchy due to the optimization algorithm. * Fixed a problem with the hierarchical data structure which didn't combine pins which we have both a logical and physical view. * Fixed problem in router with misalignment of via. While it wasn't causing a design rule error, it was making ugly routes. * Added point quad and dset Tcl modules to help with advanced Tcl programming. * Added -flush option to icrecord to flush statement to file. * Added the -pin option filter to icinstance binding command and added the -filter option to icinstance get command. * Added the icdesign_name and icread_routing command to the igp floorplanner. * Added the capture_exec_cmd so we can capture the screen from a script. sigma : Feb 24, 2009 * Improved floorplanner support of clustered constraints. * Added ability of floorplanner to read detail routing in addition to prerouting. * Added environmental control of memory manager on Linux 32 bit machines. rho : Feb 21, 2009 * Test version. pi : Feb 19, 2009 * Removed double counting of feedthrus when adding side access feedthrus. * Fixed row equalization when side access feedthrus are present. * Removed a debug statement which output an incorrect ERROR message in the Verilog parser of the translator. omicron : Feb 17, 2009 * Improved the initialization and behaviour of the igp floorplanner. Now the initial placement is free of overlaps. Also the initial placement now has properly placed ports. * Fixed problem with simplify not passing initial fixed constraints to the placer. This was causing the cost_only option in the placer not to work properly. Instead of calculating the cost of the initial placement, it was calculating the cost of a bin packed placement. xi : Feb 12, 2009 * Fixed syntax error which was reported erroneously. * Fixed problems with binding errors in the Verilog parser when positional parsing is employed. * Added debug mechanism for displaying initial configuration. * Added more debug information to icread_spef command. nu : Feb 10, 2009 * Support for side pin access when clusters are present. Does not work for hierarchical clusters yet. It will in upcoming version. mu : Feb 6, 2009 * Added missing code to the net TYPE mechanism. Now the net type is output to the constraint file if it is defined. Also output the created net attribute if it is et in the translator. * Fixed a major problem in the placer with port (aka switch) optimization when timing constraints are present. Timing constraints cost function was missing an assignment and this caused the cost function to evaluate true regardless of wire length. * Fixed a crash in the global router due to an improperly freed feedthru associated with a spacer cell. lambda : Feb 5, 2009 * Added code to enable the debug of side access pins in the global routers. * Fixed problem with detail router not obeying the PIN_LOGICAL attribute. * Added the -include_models and -exclude_model options for the translator command icwrite_placement. This allows us to easily sift out unwanted models such as feedthrus. * Fixed crash when icmake_default_feedthru is placed before a physical library is read. Now it may occur first. * Improved the VHDL writer in the translator. Added -ignore_ports, -implicit_global, -ignore_layout and -no_components options to the Tcl command. * Now SPEF reader has mechanism to expand nodes when cross referencing replacement gates. * When writing SPEF we output the components in sorted order. * Added the -absolute, -raw, and -database options to icmodel pin command. kappa : Feb 2, 2009 * Improved side pin access capability of the global router. * Improved the handling of bus nets. Added the icnet bus Tcl command to manipulate bus nets. * Added support for x and y path weighting factors for length constraints. Previously this was only available for the other timing constraints. * Added ability to add a header and trailer to DSPF output files. * Added icwrite_verilog spef command in order to output SPEF strings according to the proper escape SPEF sequences. * Added ability for icconstraint Tcl to handle PATH constraints. * Fixed problems with the -literal option in the Verilog parser. * Fixed problems with the icnet rename command when [] are present. iota : Jan 27, 2009 * Added side_pin_access_file support to the global routers to allow user to specify side pin access. * Fixed crash in detail router parasitic extraction code. theta : Jan 21, 2009 * Fixed problems with a crash in the placer when standard cells are modeled as fixed hardcells. * Now parasitic analysis code is common between the detail router and the translator. In addition, the SPEF data structure is now consistent with the DSPF data structures. * Added icdesign init function so we can create a design from scratch, that is, without reading any files in the translator. * Added the -pintype option to the icmodel addpin command and added the -capacitance option to the icmodel addport command in the translator. * Restored the ability of the Verilog reader to create a dummy library if models aren't supplied. eta : Dec 31, 2008 * Added the global net TYPE constraint to the constraint file so user can designate power and ground nets. Added ability to script this in the translator using the icnet globalbind -type command. * Added a few more Tcl commands: icinstance basename, join, and parent commands. Also added icmodel instances -netfilter option. * Added the icrows::get_design_rows so one can get the number of rows in a previous run during ECO flows. * Added the icflatten_netlist -iref Tcl functions so one can explore a hierarchical netlist. zeta : Dec 19, 2008 * Added BUSBIT attribute to library pin and _BUSBIT_ attribute to circuit file to annotate the pins of busses. In addition, module I/O list is now in same order as input Verilog. * Now iroute calls idetailer in parasitic graphics mode when not in parallel display mode. Now user can gain graphics control of the detail router when iroute is called from a flow (in single processor mode). * Now icvias add command can take multiple cut geometries. Previously, it was erroneously limited to one cut. * Added the -inst option to the icmodel instances command for convenience. * Fixed a problem with min area design rule in the gridless router. More work still needs to be done. * Now we don't write out layout cells by default when writing Verilog. * Added the ability to perform filtering when manipulating constraint files in the icconstraint Tcl module. epsilon : Dec 9, 2008 * Added ability to show/hide fixed cells in the translator. * Added the depth option to icplacepads::beautify command so we can get better results. delta : Dec 4, 2008 * More improvement to vertical row placement. Fixed overlap problems for all overlap modes including gate array. Now default gate_array overlap mode is allow_space since it makes the most sense. gamma : Dec 2, 2008 * More changes to make vertically oriented rows run more quickly and with better results. The execution time is now related to number of moveable cells rather than total number of cells. * Added the allow_uneven_rows parameter to the placer. beta : Nov 28, 2008 * Fix for overlap of double height cells in the placer. alpha : Nov 26, 2008 * Added a more sophisticated row extension algorithm in the overlap routines. Now standard cell macros should map to the correct rows. * Fixed logic mistake with ignore_keepouts parameter in the floorplanners. * Made core macro transparent when model_fixed_rows and cover_cell_transparent are enabled. * Added test to floorplanners to see if overlapping double height rows are present and output appropriate output error messages. * Fixed crash in placer when double row definitions are not consistent. z : Nov 20, 2008 * Now row adaption supports vertical rows for completeness. * Fixed gate array option for vertical rows. In addition, spacers can be added to these vertical rows properly. * Added ability to simplify DSPF to a simple lumped circuit if desired. * Moved icmodel foreign command to general and common icmodel commands. * Now all Tcl-based programs have access to this command. * Added icfix_instance and icrow overlap commands to iroute program. y : Nov 8, 2008 * Now Verilog reader check to see if instance model has been defined in a hierarchical model when reading in a netlist. * Added the -simplify and -nets options to icparastics::write_dspf command. * Updated icspice::write command so that it outputs Spice subcircuit in proper model order. * Added the icmodel nets command for completeness. * Now icnets::driver_check looks for floating inputs on gates. * Fixed a problem with an infinite loop in the placer due to a bug in the implementation of split row double height cell code. * Fixed problems with complex double height rows. Code was rewritten to insure that complex cases are handled properly. * Now accept STDCELL as a valid alternative to STANDARD in the .lib file. x : Nov 5, 2008 * Added the icmodel instance -delete command. * More improvements and checks to the genrows algorithm. This includes a fix to scaling of rows. v : Oct 31, 2008 * Now we handle user defined overlapping rows much more gracefully in the floorplanner instead of seemingly entering an infinite loop. Now we output a much more meaningful error message after we have tried for some time to remove overlaps. This can happen when the user row definitions are hopelessly wrong. * Improved exact pad placement algorithm. * Improved the icrow Tcl command and added icrow add subcommand. * Fixed a problem in the clustering program where the netlist impropely wrote out a hierarchical netlist. * Improved the behavior of the pad placement code in the detail router as we now properly ignore cover cells during pad placement. * Added Draw Cell Type to ifp. Add tile info command for parasitic mode in translator. Added All Models On/Off to the standard cell placer GUI. * Added ictrace::report_models and ictrace::replace_models in order to perform crude model sizing. Added -maxlen option to DSPF generation and now default width is 80 chars wide. * Added modeling of fixed row data in floorplanner (keepout regions are still incomplete. * Began work on a DSPF parser which will read in and display a DSPF file. This included the new icread_dspf function in the translator. * Now we properly 2 point output rectangles when writing dummy models in the translator command icwrite_gds2. * Fixed problem with reading Synopsys library files. Previously, errors were generated stating that it didn't understand timing type. Improved the output error message as well. * Added the -msb_to_lsb option to icwrite_verilog so we can change order of array bits. * Added the icmodel modifypin command so we can modify a pin. Added accompanying command icpin modport command so we can alter port properties and geometries in the translator. * Added icwrite_verilog module_context function. * Improved parasitic extraction such that sliver regions are minimized. * Fixed problem with wrong endianess in processing assignment statements. This was a major problem and caused LVS errors. * Avoid crash in row-based placer even in cases where row definitions are invalid. Improved running time behaviour of row-based placer when only vertical rows are present. u : Oct 9, 2008 * Added max_classes parameter in order to control the number of classes available. * Added precision_row_control option to constrain row lengths to very tight tolerances. * Began work on incorporating 45 support in detail router. * Rewrote the icgds begin_conversion and icgds end_conversion command so that layer names can be processed properly as initialization will be performed. t : Sep 30, 2008 * Fixed problem with detail router crash when global net is not properly defined and number of ports is much greater than 2. * More improvements to lonely via processing. s : Sep 27, 2008 * Added the max_width option to the global routers. This new feature allows the user to constrain the width during area minimization. Added documentation for this feature to EZ and fixed mistake in feed_search documentation. r : Sep 26, 2008 * Fixed problem with design rule errors in mesh network when prerouting has bends in distribution trunk. * Fixed problem with missing feedthru processing which caused crash in global router when only one feed port was presented by user in library file. * Improved the ability to place relative pads in the I/O editor. Now code moves pads if they are on the wrong side and are relative. * Improved update of pad information in the I/O editor GUI. * Added the -transfer option to the icrestore_hierarchy command so we can propagate any modifications made to the flat netlist into the hierarchical netlist. q : Sep 15, 2008 * Fixed a logic problem in the memory allocation of the power and ground network. The fix results in a major improvement in memory usage when large power and ground networks are present. * Fixed two design rule errors with respect to samenet via processing. Previously, some stacked vias were not properly stacked resulting in samenet and notch design rule errors. * Improved lonely via code. Now post processing is done automatically. * Added the -nolonely option to the icoutput command in the detail router. * Added the iclonelyvia command to the detail router to allow processing at any time. p : Sep 12, 2008 * Fixed a crash in the global router when the number of ports associated with a pin becomes very large. * Added the ability to control model type drawing in the global router. * Added the ability to sort by number of pins on a net in the itools routing statistics tool in the translator. Fixed problems with scaling length. * Fixed crash in detail router when global net is not defined properly. * Fixed problem in translator parasitic code when generating DSPF and the pin has electrically equivalent pins. Previously, it was errorneously complaining that the net wasn't connected. o : Sep 9, 2008 * Fix of detail router which caused an infinite loop during prerouting. * Fixed a problem which left some nodes of the parasitic graph without an edge. n : Sep 7, 2008 * Major rewrite of timing code. This was necessary to insure complete consistency with Synopsys. * Added support for lonely via design rules. * Added full support for spacing tables. Previously, they existed internally but now uses have full access to them thru the translator. * Added ability to control output of timing table types to itools library format. * Added support for CLOCK pin attribute in the itools library. * Added Tcl stack package module icstack. * Added initial support for SDF condition statements in timing tables. * Added a trace tool and a routing statistics gui tool to the parasitics context in the translator. * Fixed LEF translator bug which translated TRI state outputs to bidirectional type instead of output type. * Now we support Verilog with empty port bindings. In addition, we also support assignments to 0 and 1 (in addition to 1'b0 and 1'b1. * Added the -replace_flattened and -flat_instance so we can manipulate the output of netlists during translation. Also added the Tcl command icnets::dump_instance_bindings. In addition, added the icrestore_hierarchy command. These options and commands allow one to restore hierarchy to the Verilog after place and route and the netlist has been modified (for example, due to scan chain reordering and buffering). Unfortunately, it is nontrivial to script. * Updated the icmodel get command so that the new -all switch returns all models including hierarchical ones. * Added error checking for the -header option to icread_verilog command. Now the command outputs an error message which the proper module name is not suplied. m : July 30, 2008 * Fix for global router port error. Global router was outputting erroneous error messages. l : July 23, 2008 * Researchers version. Updated spice.tcl. Added icdesign_name to iplacesc. k : July 18, 2008 * Fixed problem with 3d ports/switches not being placed properly. This failure occured when there wasn't any conflict between the switches and the cell library. The code erroneously thought there was nothing to do. * Improved the 3d port placement result when the core is small compared to the average cell width. j : July 17, 2008 * Fixed problem with version 40i not building properly. That version has been removed. * Improved the icbeautify command so that it removes artifacts when ripup depth is greater than 0. * Updated the EZ documentation so that prerouting is documentation is up to date. i : July 15, 2008 * Added missing code to implement cell gridding throughout itools. Gridding is specified in the parameter file. A new option called gridto allows the user to set the cell reference. The gridto may be either center, lowerleft or foreign_offset. Pad placement was augmented to grid in both directions. * Added the ability to draw vias in the translator as a convenience function. * Improved the behavior of the compactor when encountering difficult compaction problems. * Improved the 3d port/switch placer by modifying the annealing schedule. * Fixed 1 of 3 problems with icbeautify. The remaining will be fixed in next rev. h : June 24, 2008 * Modified EZinstall so that it checks to see if csh exists. If it doesn't exist, then it attempts to complete with the Bourne or Bash shell. * Added support for ignoring `ifdef definitions in Verilog. * Fixed a few minor problem in the gridded router when running on the Sun. g : June 5, 2008 * Fixed another crash with the clustering constraints. This crash occured in the translator. f : June 5, 2008 * Fixed a major problem with clustering constraints. We now avoid a crash in the clustering program when cluster instances are missing. * Added ability to draw clusters in the placer. Use Highlite Clusters option under the Edit Menu. * Added initial support for abort_subprocess parameter for debugging placement program. e : June 5, 2008 * Fixed problem with aspect ratios not being properly propagated in constraint files. Also added verbose debugging to syntax checker. * Added the iccreate_abstractions design command to build an routing abstraction to be used at the next level when itools is used to build blocks. d : May 29, 2008 * First cut of the detail router script editor. Still needs work to improve look and has not yet been put in the default GUI configuration. * Improved the performance of generating a statistical report in the detail router. * Improved the information of icnets::distribution to include number of nets and pins present. * Added the CLUSTER SUPPLY constraint so one can define multiple power supplies in an alternate way. This method is an alternate method from PARTITION_SUPPLIES. PARTITION_SUPPLIES works based on the supply nets bound to instance. The CLUSTER defines the set of instances in a power supply object. * In the cluster program, we now alert the user when rows haven't been defined. Also improved the robustness when clusters are present. Fixed problem with class constraints not being obeyed. * Now buffer synthesis code can run without timing data if the new parameter buffer_timing is turned off in the parameter file. * Improved speed of table output for large Tcl print tables. c : May 12, 2008 * Added ez:close_connections so we shutdown open process ids if EZ is shut abruptly. This prevents run on programs. * Fixed problems with notch filling when netlist is uncontracted. The notch filler was converting the entire mega net into the first net segment index. This resulted in the disconnection of the net - a major problem. * Now support multiple timing delay records with different unate properties. This was necessary to support exclusive or gates properly. * Now we test the license server in the translator when doing prerouting so the user will know if there is a problem with the license server. * Fixed problem with clock spine configuration when in flat placement mode. Now we draw the clock spine better in the placer. * Fixed a minor problem reading Spice data. Added the -tieoff_lo and -tieoff_hi options to the Verilog translator to aid when file uses 1'b0 and 1'b1 to tie off gates. * Added the icmodel instances -nets switch so we can list the hierarchical models from Tcl. * Added the out of order switch to the icread_verilog command so that the user is not required to add Verilog in the defined before referenced order. * Added icpin command to translator. Also now have the ability to control output section of the DEF write command. * Many improvement to EZ. Now startup initializes scripts in the proper order when starting EZ from command line. In addition, more button are smart in that they change color when data gets out of date or files do not exist. In addition, the detail router will not fire until all inputs are generated. * Now we can detect user added row straps during power and ground construction. This allows use to add row straps and make use of them properly when we build a power ring or stripes. * Fixed major problem reading routing constraints. All previous pre40 versions had a bug which prevented reading of the region routing. * Added experimental full chip routing compaction to the detail router. Still needs more work but the initial results are promising. This compaction is similar to region compaction algorithm. * Added the iclex -strip_comments command so we can efficiently strip C, C++, and shell comments from a file. * Improved the graphics zoom function so that large zoom out factors work properly. * Added the -g graphics switch to twflow to make things consistent with itranslate. * Now reassign limit may be zero in the global router. It was erroneously limited to one previously. * Improved the output of the constraint reader when in echo mode. * In the translator, we now draw the outline properly for ports. Previously, fill was turned on when outline was requested. * Improved the icread_cons -filter function and added the -match option to support both positive and negative logic. The improve functionality was necessary to improve EZ. * Added the -wires_to_pin option to the icread_lef command which treats obstructions connected to a pin as wires and traces them so they become part of the pin itself. b : Mar 24, 2008 * Now we support name lists in Synopsys liberty files. Previously, this was parsed erroneously. * Updated the DSPF code so that it no longer longer requires the graphical mode. * Updated the gridless router so that it can even fix connections to pins which don't meet the minarea design rule. The gridded router still follows the assumption that pins meet the minarea design rule. * Began work on generating formatted static timing analyzer reports. This work will be completed in next revision. * Updated translator abstraction Tcl so that it now supports the -enumerate switch when using the simple_only switch to icabstract command. * Added the itools_table Tcl module so we can output a formatted ASCII table. This was useful module to create static timing analysis reports. * Added the icsta clock command in the translator to facilliate proper operation of sequential circuits. * Added better error messages when flattening instances. Now we report offending instance where possible. * Now we calculate the default min pad spacing by analyziing the pad models. Previously, the default was 0 but often this would cause design rule errors during routing. The user can still set the value explicitly but now the default avoids problems downstream. * Rewrote the CLOCK constraint to work with the static timing analyzer. * Fixed a repainting problem with the contour detail router. In some cases, routes weren't completed due to missing data. While the router would eventually the nets properly, this problem slowed convergence of the routing. * Now we don't report via coverage errors of pins when pin errors are turned off. This makes the via coverage rule consistent with other rules. * Added NMOS and PMOS models to the list of models whose placement can be fixed. * Added the -45 and -all_angles options to the icpickpath routine. * Rewrote the 45 degree drawing and intersection code so that GDS2 with 45 degree angles are properly drawn and translated. * Updated icread_lef option -remove_pin_obs so that it now is more careful in removing keepouts around pins. a : Feb 23, 2008 * Rewrite of the icread_synopsys command so we can correctly parse the Synopsys library format. The static timing analyzer was improved and now gives the correct answer for combinatorial circuits. Sequential constraints will be fixed in an upcoming version. * Updated DEF so it reads pin properties correctly. * Now we can control the precision of the libraries delay data from the translator with the icwrite_lib precision command. * Fixed problems with padgroup constraints in the iroute program. * Added icinstance remove_type command to remove filler cells. * Improved the ezredir Perl script to automatically create a backup file. * Improved EZ documentation system so that it cleans files properly with the new itoolsdata structure. Now allow translation of multiple GDS2 files in EZ. * Fixed msg initialization problem in placepads::check_overlap. Version 2.0.0 pre39 ======================================================================== : Feb 14, 2008 - code freeze version 2.0.0pre39. Now in beta directory. y : Feb 6, 2008 Added cluster_priority keyword to the placer. This allows the user to either allow clusters or fixed constraints to dominate when both refer to the same instance. The default is for fixed constraints to dominate, that is, clusters will be ignored for any instanced that has a non-trivial fixed constraint. A trivial fixed constraint is an initially fixed constraint. Fixed a problem with compact_cell overlap algorithm which did not proper set the starting position on a manufacturing grid. Updated icobstacle::grid_point idetailer Tcl so that we check to make sure that a grid is defined before attempting to grid coordinate. Updated iccost_state:save command in the detailer router so that missing cost components are all now saved. Added missing gridding to the iroute program. x : January 31, 2008 Fixed a problem with incorrect output of the new cluster splitting code. Previously split clusters had random output. w : January 31, 2008 Fixed a crash in the the new cluster splitting code. It happened when the clustered cell has orientation 2 or 3. Updated the scan code to make the output net name correct if at all possible. v : January 22, 2008 Now we automatically split clusters which are longer than the length of the into two pieces. Now we properly reference Verilog models with leading backslash to the cannonical form found in the library with leading backslash stripped. Fixed problem with outputting the wrong pin name when generating DSPF. Fixed several netlist writers so that they handle multiply bound pins (must connects) properly. Previously, they worked but output annoying false error messages. They include the def writing in the translator and iroute. Added the DISTRIBUTE_MODEL option to the buffered net H-tree algorithm. This will allow the user to supply any driver model to the center distribution driver including a null driver cell which just provides routing. Fixed "ERROR[ADD2SET]:value of node is out of bounds of set" problem which was due to a row class assignment problem. Added the iclicense::available command so you can stop a program if the license server is not available. Added ability to draw standard rows in the translator. Improved and fixed the icswap_coordinates function so that it now properly orients routing and pads. Added the -toplevel option to the icwrite_def command for completeness. We now keep track of vector wires when outputting Verilog. Added icinstance remove_spacers to support gate_arrays properly. Fixed problems with icmodel boundary command when modifying the boundary. Offset was not properly calculated. Fixed problem of moving rows when no cells are present in a row when in gate array mode. The program iroute was modified to fix the problem. Fixed problem with crash when manually added routing in the idetailer program. Added the icscanpath command so we could draw scanpaths in global routers. u : January 22, 2008 Added more debug to the Verilog translator so that it gives better error messages when binding mismatches occur. Also fixed a problem binding Verilog signals when two leaf instances have bus signals. t : January 17, 2008 Added the icwrite_verilog dictionary commands which create and maintain a dictionary of all identifiers where all special characters that normally need to be escaped in Verilog will be replaced with the underscore character. The facility will maintain a 1-to-1 mapping between the itools cannonical names and the modified names so that no shorts or opens are created and that an inverse operation is possible. The Verilog writer, the Spice parasitic routines (including DSPF) and the SDF writer all now automatically adjust their output if the dictionary command is present. Fixed problem with hierarchical foreign offsets. Previously, the foreign model offset was not applied properly. Added the -antenna option to list antenna attributes when displaying bound net pins for the icnet binding command. s : January 11, 2008 New hierarchical pin optimiziation algorithm has been added to the igp floorplanner. Eventually, this floorplanner will be extended to allow full hierarchical placement. Also added the cover_cell_transparent option to allow different defintitions for the cover cell. Added a missing function in the itranslate program which will allow the icalert_user dialog box to work properly. Also added the -graphics switch to the icalert_user dialog box so that it can start the graphics system if needed. Otherwise, it just sends the message to the defined message system. Added the icplacepads::check_overlap command in the translator so we can check user data when exact pads are present. r : January 9, 2008 Improved the behavior of the strap router. Now vias are properly array and now the router makes use of generated vias if such information is available. Fixed a bug where hierarchical models were not output in the translator. This resulted in syntax errors. In addition, fixed a crash when an expression was present in the Verilog. Added the parasitics graphics context in the translator to facilitate the generation of DSPF (Detailed Standard Parasitics Format). While simple combinatorial cases work properly, more complex circuits are not output correctly yet. This will be fixed in a future version. This was implemented by the new icnet parasitics -graph command. Fixed a problem in the iroute program which prevented the proper transfer of antenna rule information such as gate and diffusion area. Added the icinstance isa_io Tcl command so we can properly discover itools generated IOs when writing foreign netlists such as Verilog. In addition, the icinstance bind command now properly outputs globally bound signal pins. Fixed problem with missing commands when starting graphics from a script when the program was not started with graphics. q : January 4, 2008 Added the _ICASSIGN_ statement to the itools circuit description. This was added so that scan paths can correctly constructed and be correctly described in Verilog. The scan path algorithm was augmented accordingly. The assignment was necessary when IO pads connect to intermediate points in the scan chain. The resultant scan chain could have two IOs on the same net which would require an assignment statement. p : January 1, 2008 Fixed a design rule error (samenet stacked via rules) in the gridless detail router. This was due to the path straightening code which aligned stacked vias. Now we supoprt the -implicit_globals switch in icwrite_verilog command. In addition, we now no longer write globally connected pins into the netlist when icglobal_nets is false. Previously, some globally connected pins were output. o : December 30, 2007 Fixed problem with crash in new strap router in the detail router. Also added the ability to draw cell types in the detail router. n : December 28, 2007 Added the icstrap command to the detail router. This command straps two adjacent layers together with vias. It was added to facilitate the generation of power and ground networks thru Tcl scripts. Added minimum height discriminator to the power mesh code in order to be consistent and flexible. Modified the stripe code to automatically connect multiple global pins. Added the -noiclib option to the icwrite_lib switch so we can make a cover cell include file. m : December 24, 2007 Now the floorplanner properly places unconnected pins on the edges of the soft macro cell. Previously, it was erroneously putting them at the center of the cell on top of one another. Now static timing analyzer understands so that it understand multiple I/O pins connected to the same signal. Fixed problem in iopad cell generator which was causing a small design rule error due to manufacturing grid. Added the icmodel pobject command so that the user can properly connect and select multiple pins with the same pin name in the Tcl interface. Fixed a bug in the icmodel addport command which prevented the proper coordinates from being entered. Added the -allow_empty switch to the Verilog parser in order to accept an empty Verilog structure, that is contain no instances. Ordinarily, this would be an error but this is useful for testing and creating the itools I/O interface. Rewrote the escape mechanism in SDF and Verilog writing routines so it properly matches the Spec and the EZ documentation. Updated so that cover cells are properly ignored during pad placement. This allows the overlay cell to exceed the pad placement area. Fixed a problem with relative pads in which the coordinates were not properly set. Ran into the biggest weakness of Tcl - the need for an expand function which is currently in Tcl 8.5 and not in the current used by itools stable 8.4. Now we could upgrade but they still haven't made up their mind on the finality of the expand function syntax. To get around this we added a workaround for the parts of lists that need to be doubly braced so the list remains valid when eval strips away one level of braces is removed. This function is called the icadjust function and now is available to all Tcl programs. Added support for modifying labels and added the structure rename command in the GDS2 translator code. Also now support drawing of a particular model type in design mode. Improved behaviour of static timing analyzer. Added ability to modify loads at internal nodes thru Tcl for testing purposes. Updated scan discover command so that it works with cover cells. l : December 14, 2007 Now the generated buffer cell instances use _ instead of : in their names so they don't create an SDF conflict. Added the convert_cover_to_pad_pins Tcl script to change cover cells to pads when necessary. Added the ::icplacepads::pad_pins function to the translator for convenience. Added icvar_set and icvar_unset in order to make user scripts more readable. Rewrote routing attributes so we can support more attributes to prerouting. Now we support the FLEXIBLE attribute which will be used for rubberbanding wires. Began support for generating VIA rules. Not complete. Improved the PIN IGNORE constraint implementation. Now it is used to ignore pad connections (when requested) and to improve the scan chain optimization. Added the icmodel pin -foreign option for completeness and convenience. Improved graphics display in iroute. Now the net order command in the detail router takes a port argument to allow unambiguous connections. Improved support for pattern vias in detail router. Pattern vias can now be used in scripts to construct power and ground networks. The translator can now describe and manipulate the pattern vias. k : December 8, 2007 Added the ::icmesh::build_flexible_mesh command to automatically extract power and ground mesh and prepare it for routing. Fixed problems with retain replacement policy. This bug was introduced in version 39i. It caused the introduction of double geometries which eventually crashed the global route after thousands of errors. Added icreplacement_policy all to make it easier for the user in the common case. Improved on the write verilog command. Now it automatically recognizes the itools port/pads which are added automatically to a verilog netlist. Added the icnet intersect function in the detail router so we can automatically build a flexible power and ground mesh network. Added ability to control drawing the various cell types in iplacesc and igp. Eventually, this code will be migrated to all programs. j : December 3, 2007 Added the ability of the gridless detail router to route pin-to-pin connects in a manner which will be suitable for simulataneous routing of signal and power nets. This should be a big win in terms of area. The finished version will be in the next version. The user can now control the connections of pins with the icnet order command. Fixed problems with prerouting model in global routers. Added ability to draw axis, core ring, and pad rings to placer, floorplanner, and translate programs. Fixed problems with PAD_ALIGN constraint. Now we can change setting for the translator and we fixed typo problem that caused syntax failure. Fixed translation problem with multiple cut layers of a via. Previously, they were incorrectly lumped into a single geometry. Fixed design rule problem with asymmetric vias. Internally, the vias were placed correctly. They were just output at the incorrect coordinates. Added path support to itools edit objects. This was done to support the manual creation of centerline paths in the detail router. Updated itools flattener to properly expand any bus definitions in models below the flattened level. This is to facilitate proper hierarchical optimization during floorplanning. Updated the Power and Ground Network documentation in EZ to reflect the capabilities of the tools. Now both cell-based and primitive-based mesh networks are supported. i : November 30, 2007 Fixed translate problem with icgds_define command and nimplant layers. Added ability to dump a set of models to the icwrite_lib and icwrite_lef commands. Added the icreplacement_policy foreign command for completeness. Fixed the icreplacement_policy keepout merge command which was improperly coded. Fixed the icreorigin translate center command. Added the icrule SPACING LOOKUP command. Aded iclayers manufacturing_grid commands as well as iclayers up and iclayers down, icvias routing_layers, icvias default_up, and icvias default_down. These commands were added to facilitate the ability to generate a power and ground mesh cell from the feed/fillcell definition. Now we check to see if the global nets have the CREATE flag associated with the net. Also added the icnet create Tcl command. h : November 23, 2007 Added the icconstraints::instantiate_model for convenience. The function allows a model to be instantiated and placed at a given coordinate. Improved igp floorplanner graphics so that it can display hierarchy properly. Now we output all of the coordinates of a hard pin on a soft macro cell. Previously, only the first point was output. Updated the model instance placement code so that all coordinates are relative to the center of the cell. This makes everything consistent. In addition, we fixed a problem with erroneously truncating the model instance list when an instance appears in circuit description but not in the physical description as a fixed entity. Now we build and maintain scanpaths in order. Previously, the order could reverse which makes things confusing. In addition, the .scan file is now a valid constraint which can be read into itools using icread_cons and display the path graphically. We added the ::icscanpath::display command to the itranslate GUI. Added the icinstance pin_netid command for completeness. Fixed problems with icsizer bloat_shrink procedure. Subtraction order was mistakenly reversed. Fixed problem with cut keepout violations occuring over virtual keepins in the region router. Fixed problem in generating the PRESENTATION record in GDS2. g : November 19, 2007 Fixed problems with the translator not outputting correct netlist when in hierarchical mode. Fixed a problem when calculating the proper foreign offset also when in hierarchical mode. Updated icextract_fix_model_instances so that it only changes the type of the fixed constraint if such a constraint has already been generated. Fixed problems with the syntax of the SDF file when in the static timing analysis mode. This mistake was introduced as a new feature in version 39f. Added the ability to program the version and generations of the output GDS2. Rewrote the scanpath code in the translator so that it now supports the icscanpath complex command. This allows one to describe multiple gate scan paths definitions. We also added the findpairs subcommand so we can find all of the available scanpair paths automatically. Now the translator command icwrite_verilog supports a filter function and a header rewrite function. The user has complete control of the rewrite of instance, model, and net names. In addition, we added the -header option to the icread_verilog command so we can write out the top level Verilog definition. Fixed problem with Synopsys function parser in the translator. f : November 11, 2007 Added a new cell origin option to the fixed constraint definition. This option allows one to use foreign origins directly. Now it is easy to convert to Cadence since you can use the Cadence coordinates directly. We added support for system timing checks in the Verilog. Strictly speaking this should occur in structural Verilog but it now may occur. Itools will simply parse it and ignore it. In addition, we added support for special case of net binding. More work on creating proper SDF data. Now we output setup and hold constraints into the SDF. e : October 29, 2007 Now we allow empty string hierarchy divider characters for more flexibility. Fixed crash when calling the itranslate icgds help function. Fixed problem with calculating GDS2 foreign offsets when bloated data changes the MCR boundary area. Added the ::icvirtuoso::define_global_nets function so now the user can remap global names to Cadence global names. Added missing trigger edge keyword to setup and hold time definitions to be consistent with Synopsys Liberty definitions and to support SDF timing checks. Now translator can read multiple Liberty files and generate min/max SDF timing delays. d : October 29, 2007 Fixed problems with extracting GDS2 prerouting data from a structure. Now icextract_prerouting will extract correct results whether the prerouting_model cell exists or not. In both cases, we will interpret the data as wires so bloating may be properly be applied. Previously, in the default case, the boundary of the prerouting cell was incorrectly calculated when no user boundary geometry was present and the MCR was used as a boundary. Added the -wire option to the icmodel add keepout command. Improved the sizer in the translator so we can do single layer operations easily. Added shrink_bloat Tcl so we can easily combine NWELL geometries in a script. It was possible previously, but this minimizes the amount of user code in a very common operation. Added the -script option to icsizer exec as a convenience to make scripts shorter. In addition, the sizer won't crash if the rules contain errors. Now the ICLAYERS keyword may occur in the input layer definitions as a convenience but with the caveat that it must be the first layer definition. This requirement is enforced by the BNF syntax. Fixed a problem in the contour detail router which prevented routing a valid stacked via configuration. Fixed a crash in the placement program that occured when model instances occur in a standard cell model. Added new features to the icsta command (static timing analyzer). We now support integration into SDF as a timing calculator. Also added the icsta dump and icsta trace commands for debugging. Added the -sta option to the icwrite_routing_sdf command so we call the static timing analyzer to calculate the delay times using Synopsys delay tables. Fixed a problem reading Synopsys library files when the function contained &. This version of the AND function was not supported previously. Now the verilog translator will look in the defined library models in order to resolve model names, specifically, the translator will look thru the list of module instances in order to determine model definition. In addition, now the Verilog translator correctly translates models with generic Verilog names such as and, or, xor, etc. The itranslate flattener will attempt to transfer any fixed constraints in the top level module to the global scope. c : October 21, 2007 Added support for arrayed vias in itools. The array construct has been documented in EZ. In addition, the cct translator now supports translation into the itools arrayed via construct. Added the viarule spacing rule in order to support arrayed vias. This has been documented in EZ. Now we use iclayers manufacturing in the Tcl power/ground ring code in order to tame the Tcl roundoff problem. Added the icsta command to the translator. This command will implement a static timing analyzer in the translator. It will borrow common code from the placement engine. The command is currently incomplete. Added the iccct orient command so one can convert between itools and CCT orientations. Fixed problems with expanding macros in Verilog. The macro expander was implemented backwards and this induced parsing errors. b : October 11, 2007 Now we support rotated vias in the prerouting data. This has been documented in EZ. Fixed problem with moving fixed ports in the placer. The problem occured while using port algorithm number 4. Improved prerouting support translation for CCT format. Now translator understands arrayed and rotated vias properly. Added support for the -exit_on_error option to the icread_spice2 command. In addition, this command has been augmented to handle multiple model file arguments. In addition, only the first data is used for a model; all other redundant data for a model is ignored. When ordered model files are present, the program now checks and reports all models which don't have reordering data. When the new -exit_on_error option is present in the icread_spice2 command, the translator will abort the run. a : October 7, 2007 Improved the unlap algorithm for cells with rigid neighborhoods especially those with many distinct neighborhoods. Added missing va_config clause to CCT wiring in itranslate. Fixed problem with crash reading Verilog with partial designs when model is not found. This bug was created in version2.0.0pre38. Fixed problem reading GDS2 data when data should be ignored. It was improperly being added to first cell which was not ignored during a multiple GDS2 file read. Only the first object of the GDS2 structure was ignored instead of all of the objects. This resulting in binding errors. Now the compactor will not be called if all cells are fixed as it just wastes time during placement. Version 2.0.0 pre38 ======================================================================== : October 4, 2007 Now properly handle multiple merged layers in the itranslate Tcl commands ::icconstraints::extract_cover_cell_neighborhoods and ::icconstraints::extract_neighborhoods_from_routing. Improved the initial neighborhood placement algorithm so more cells are placed within their neighborhoods. Updated placement prerouting code to include missing via code. Fixed user extensions in itranslate LEF code reader. Now we prevent a crash in the gridded router when routing areas near the boundary of the grid. Also fixed design error in the gridded router between routing and unconnected pins. Now support via options in the CCT .wir format. Added the icrow rowsep command to itranslate so we can calculate average row separation for the user. Augmented the Verilog reader so that it can read out of order Verilog, that is Verilog where things are referenced before they are defined. Now we tell the user when they didn't set the flow when generating the grand.do file in EZ. Now prevent tiny slivers from forming when editing the placement of instances. gamma:26 September 2007 Fixed out of order statements in placer which caused crash when port algorithm #4 is enabled in hierarchical placement mode. beta:25 September 2007 Now we check to make sure that we don't create a rigid neighborhood smaller than the width of the cell. This was occurring in the itranslate Tcl routine icconstraints::extract_neighborhoods_from_routing. We also modified the placer to remove any invalid neighborhoods which are too small for the given cell width. We improved the initialize random placement algorithm so that rigid neighborhoods were properly observed. Also fixed typo in neighborhood report. alpha:19 September 2007 Added missing -toplevel option to the icread_spice2 itranslate command. Also put WHATSNEW file in reverse chronological order for easier reading. z:18 September 2007 Now translator can draw routing, keepouts, and ports with a border for better viewing. Now we avoid error message in icwrite_routing_sdf when net is a power/ground net. Fixed problem with initialization of ports in the icread_spice2 command. Previously, both pads and ports were being output as the same entity. y:14 September 2007 In the Tcl procedure icnets::driver_check, we now include nets which are tied-off to power or ground as nets having a driver. In the translator, we added the -case_insensitive switch to the Tcl command icpin_type update for convenience. Also we now can write out netlist even if hasn't been flattened. Added -model_file capability to the icread_spice2 command and allow this command to read spice subcircuits out of order, that is, now they don't need to be defined before referenced. However, they must be defined once all Spice files are read. The icread_spice2 command also now takes the top level module as an argument when flattening of hierarchical netlist is desired. Fixed a problem with flattening netlists in that one extra level of hierachy was being added to the net name. Also we prevent a crash when one tries to flatten a null netlist (no data read in). x:12 September 2007 Fixed problem with replacing fixed instanced with rigid neighborhood constraints when using the extract_neighborhoods_from_routing. Fixed problem with icadd_keepins delete command deleting user added keepouts. Fixed problems with Yvector_alloc messages when prerouting is present. w:12 September 2007 Added the -region option to the icdesign_name command in the detail router. Fixed problems with restoring user added keepouts during region compaction. User added keepouts would dissappear during compaction. Other keepouts were not affected. v: 7 September 2007 Changed internal fixed constraint structure namely neighborhoods so that we maintain original constraint so we can visualise neighborhood constraints. Added rigid neighborhood support to the fixed instance GUI. Now we also throw away invalid neighborhood constraints when the neighborhood does not intersect a standard cell row. Fixed problem with upper right boundary of neighborhoods. They weren't getting adjusted properly. Edit cell now user to visualise the neighborhood constraints. Use the Advance button to display GUI. Now we pass prerouting to placer so we can perform proper overlap removal when we perform port placement. Previously, we didn't read prerouting into the internal database. Added the ability to draw prerouting in the placer. Updated the return Tcl list from the icfix_inst get command and added the -adjusted and -neighborform options. Added the ability to make the itranslate command icgeometry use maximally vertical tiles through the use of the -max_vert options. Fixed the icpadgroup help command in the translator. Added the icplacepads::extract_side_padgroups so we can generate padgroups from a given set of pad placements. Added the compact_ports autodetect mode which determines the port layers from the layers found in the referenced port cell models. Added merge_port_layers option to the placer so that user has control over whether all ports are placed at the same time or ports are placed on a layer by layer basis. Improved the results of 3d simulated annealing port placement aka cport algorithm #4. Fixed problem with design rule violations using this algorithm. u: 29 August 2007 Now itools automatically inherits pins from subinstances below the placement object. So in principle, the user could have subplacements with pins within standard cells. This is most useful for large complex macro cells. In addition, models no longer need to be defined before reference in the library file although it is still encouraged. However, they do all need to be defined at the end of a library definition. Fixed problem with %INCLUDE file in reading parameter files. Now translator can handle designs with no via geometries if require_vias is off. Updated graphics in itranslate so it can draw hierarchy in the model view. Now the translator can read incomplete verilog designs using the new -partial option. This is useful in floorplanning. Added the -unnamed option to the icmodel foreign command in the translator. Improved the functions to the iccrossref command in the translator. Added the -physical_only switch to the icwrite_ic command for partial netlists found in floorplanning. Added an attribute argument to the translate filter of icread_verilog so one can distinguish the usage of a string. Current values of the attribute are : instance and module. Added the the -placed and -init switch to the icmodel instances command. Added icextract_fixed_model_instances to extra model instances from a top level module. Added the icvirtuoso::hierarchy command for building Cadence compatible instance names. Fixed problems with the floorplanner when complex attributes are added to a cell such as the GROUP attribute. t: 15 August 2007 Documented the license_max_tries parameter. Added the iclicense::unavailable Tcl command and documented it in EZ. Major rewrite of the fixed data structures so we can properly handle fixed and rigidly fixed neighborhoods in hierarchical designs. Fixed error message (illegal tile) in TimberWolfSC when placing ports. Fixed problem translating CCT paths. Previously width was set to minimum width instead of reading width value suppplied. Added icconstraints::extract_neighborhoods_from_routing so we can prevent placement of cells over prerouting. This uses the new itranslate "icgeometry routing" command. s: 27 July 2007 Added the icinstance remodel command so we can swap out different models for an instance. Also added the icremodel Tcl command (which uses the icinstance remodel command) and searches the netlist and replaces any instance with the given model with a new model. r: 25 July 2007 Added the *memory_messages option to the parameter file to turn off memory usage messages which annoyed some people. Now it is optional. In addition, we added the icmemory messages command to itranslate so you can turn it off in the translator as well. Documented this in EZ. Now we allow partial synopsys libraries, that is, the library keyword is no longer mandatory. Now icread_synopsys properly reads files with DOS carriage return characters. Also error messages are improved when reading Synopsys library files. q: 23 July 2007 Fixed two infinite loops present in the placer. The first loop was due to a mistake in the cluster building algorithm. The second type of infinite loop occurred when many fixed cells were present and the valid locations to place the standard cells were few. The program was not trapped in a loop but required an inordinate amount of time to find a valid position. A new algorithm has been constructed which efficiently finds the valid placement locations. p : 16 July 2007 Added timeout debug info to Expect scripts run in debug mode. Added the iclog function to ICTk so we can redirect stderr to a log file in the icdaemon. In the parallel routing algorithm, fixed a problem in reading the process id when using the icdaemon startup mechanism. This resulted in effectively removing this host from participating in the parallel routing. Now we use the full pathname for the rout.# redirect files in parallel routing. o :12 July 2007 Removed a memory leak for the floorplanner and placer when compaction is performed. Now license taginfo cleanup command works only on the userid from the requesting stream if the requesting connection is non-privledged ladmin. In privledged mode, taginfo cleanup command will removed all tagged programs and request them to reregister. Improved countdown counter so it works properly regardless where it is on the line. Fixed default prompt for the ichost startup tool. The Expect script requires \$ not $ because it will be treated as a variable and not as a symbol. Now the ichost tool only recognizes icdaemons that the user owns and reports when a login name mismatch occurs. Now icdaemon uses countdown counter during waits for prettier output. In addition, the icdaemon now removes stale suicide files so it doesn't kill itself. Added more debug to parallel routing commands. Now the addition of a second -debug keyword enables very verbose parallel debugging. Fixed problem with license not releasing after parallel routing. n :11 July 2007 Added -hostfile argument to ichost tool so we can read a host file in for the user during automatic test of the host file. Updated syntax program so that it now supports automatic testing of the host file. Added the test of icdaemon registration so we can check the license server for correct operation. Added documentation for fix_orientation_problems in the placer. m :10 July 2007 Fixed problem with parsing hierachical netlist format. Added missing keywords to parsing table. More documentation on hierarchical netlist. l : 9 July 2007 Hierarchical netlists documented in EZ. New -nogui switch to ichost command. Better error messages added to ichost as well. More ichost and -mount option in the circuitName.host file documentation. k : 2 July 2007 Fixed a problem with a low level data structure which was causing problems with redrawing data to the screen. Fixed spacing problems with floorplanner compactor. Ports were being placed too close. Added new ability to anneal ports in the standard cell placer. Use ICSC*compact_port_algorithm : 4 in the parameter file to enable this algorithm. j :29 June 2007 Fixed a problem with overlapping cells when pedestals are present in the standard cell placer. Reorganized the netlist definition so it is consistent with the flat definition. Now the netlist is contained in the .ckt file instead of the library file. Added the -hierarchy switch to the icwrite_ckt translator command. i :16 June 2007 Added Capture Screen command to EZ GUI for completeness and utility. Improved the behaviour and features of the host tool so it works better with the icdaemon. Improved the icdaemon so that it has -restart and -suicide options. Documented the use of parallel hosts for routing in EZ. h : 8 June 2007 * Fixed crash when design does not have any nets and has cluster constraints. g : 7 June 2007 * Added icexit_on_incomplete command to the translator so one can invoke graphics log reader mechanism on a failure to complete the script. * Added the -area and -layer options to ictell_tile function in the detail router so we can get info on tile data in an area and on a given layer. f : 4 June 2007 * Fixed crash when no placeable objects exist in the standard cell placer. e :24 May 2007 * Fixed problem with spice flattener due to continuation characters and DOS files. Also fixed problem reading include files and improved spice parameters for mosfet instances. d :17 May 2007 * Added the icinstance binding -instorder command so we can output a Spice netlist from the internal netlist format. * Improvement to the icrouteable command so that it detects when a route is not possible due to missing vias in the technology section. * Added the icspice parameters command so we output a spicelist from the internal itools format. * Fixed mc_compact so that it can handle negative core coordinates. * Now iplacesc shares the compactor code from igp and so now it doesn't have to fork a process to call mc_compact (old compactor). This speeds execution time when ports are present. c : 9 May 2007 * Fixed problems with merging cover cells when multiple pins with the same name exist (must join pins). In addition, the prerouter was modified to properly handle must join pins. * Added ability to control flattening by the use of model information in addition to instance control previously added. b : 2 May 2007 * Fixed problems with the icnet command in the placer, global routers, and detail router. Some subcommands were not working properly due to a conflict introduced in the last version of 2.0.0pre37. * Added net WEIGHT option to the icconstraints Tcl namespace for completeness. Added the -copy_first option to the write_constraints function so we can reorder constraints as needed. * Now overlap errors in the placer return an error and activate the graphics log reader when exit_on_error is enabled. * Fixed a problem with scaling the spacing requirements for port placement when absolute coordinates are given. Because the compactor was given the wrong spacing values, the ports would effectively overlap. * Fixed implementation of net WEIGHT constraint so that user constraints are observed. Previously, weight constraints were only accessible/generated by the program itself. a : 25 Apr 2007 * Added the PIN IGNORE constraint so individual pins may be ignored during placement. Added the icnet routing exists function and moved the icnet routing command from the translator to the dynamic misctcl library module so all programs can issue this command. Added the icnet ignore_pins commands to provide Tcl interpreter support for the PIN ignore constraint. Version 2.0.0 pre37 ======================================================================== m :23 Apr 2007 Now we store off io_port names of CCT input so we can restore them upon the creation of a .ses file. :25 Apr 2007 beta release Fixed problems with rounding positions of virtual ports. Problem was due to unnecessary floor command in the Tcl procedure. l :19 Apr 2007 Now ictile_info of the detail router takes the -center argument to calculate and display the center of a tile. The create abstraction Tcl now takes two additional arguments: -nominjog and -targetpins. The -nominjog turns off the minjog code. The -targetpins allows a via to be placed on a pin during prerouting. This was added to improve the prerouting on some older technologies which don't have minjog rules. In addition, we now allow the y position of the prerouting to be specified in the exact order list. Also we now use a more thorough algorithm in searching for the geometry to align the pin during prerouting. Added the -create_nets/-nocreate_nets options to the CCT translator so that prerouting can be read and instantiated even if it is not in the netlist. k : 6 Apr 2007 Added the ability to output pin type and pin attributes from the icnet binding command. Improved prerouting model in placer and floorplanners so that all prerouting is screened to see if the geometries should be converted to freeways. This can radically improve the results of connections to prerouted busses. Fixed problem with initializing the number of points in a path when translating from CCT. j : 5 Apr 2007 Now standard cells fixed as hardcells can now really can take on the main attribute of hardcells - rectlinear shape. This is useful for multirow L-shaped cells. Now a better error message when reading unknown components in a SPICE deck. Now we support partitioned power supplies where the user has defined the power supplies for each row. Automatic assignment is almost complete. i :22 Mar 2007 Fixed problem with overlap of double height cells in overlap routines. This problem occurred when the user fixed a double height cell in the row and other double height cells in the row could get overlapped in the row direction. Added icnets::driver_check Tcl procedure so the user can check to see if all nets have a driver. This allows earlier detection of problems rather than waiting till later in the flow during SDF creation. h :21 Mar 2007 Fixed problem in VHDL translation which added bogus interface pins. g :20 Mar 2007 * Fixed problem of outputting error messages in the sdfwrite translator command when the net contains only a single pin. * Added support for the -supply_binding option to VHDL parsing so user can map logical 1 and 0 to the power/ground supplies. This will allow users to tieoff gates to logical 1 and 0 in the VHDL yet physically tie them off to the supplies. f :13 Mar 2007 * Fixed CCT translator to understand multiple word properties. * Fixed Synopsys translator so that it understands quoted strings much better. e : 2 Mar 2007 * Updated programs so that class constraints for clusters are inherited from the member instances. * Translator now by default creates nets that the router has generated when reading the final routing. This may occur on power and ground nets which the router may have generated. Previously, these nets were ignored. d : 22 Feb 2007 * Added the icmodel instances command to the translator so one can list the instances of a hierarchical module. Updated the icread_vhdl command so that it can take hierarchical netlists and now processes assignment statements properly. In addition, the IO pins are now added properly. Also added, -case_insensitive switch which converts names and identifiers to lower case. c : 15 Feb 2007 * Fixed problem with conflict between Draw Reference and Graphics Update command in iplacesc program. * Fixed problem with poor result with small chained test case. The move strategy code had a problem which resulted in the annealing schedule aborting early after 1 iteration. b : 08 Feb 2007 * Now we alway output a model if it is used. The translator had a logic problem which prevented this from happening when hierarchy is present. a : 07 Feb 2007 * Fixed problem with translating design names that end in _#. This was conflicting with itools names for routing regions. Now routing regions will be suffixed with _R# to lessen the conflict and additionally, the -basename switch will allow the user to override the name truncation mechanism entirely. Version 2.0.0 pre36 ======================================================================== * Fixed unitialized variable in igp which was causing errors in the global router by not initializing the position of the cells properly. * Added the model type info to the iceditcell GUI and added the ability to edit the size of softcells during floorplanning. * Now take neighborhood constraints into account when we perform initial placement. * Improved quality of the detail routing by fixing a bug in the cost calculation. * Fixed problems with error messages in the placer when class constraints are present in the hierarchical mode. * Fixed a problem in the global router which avoids a crash if pins are not defined properly or are shorted together. * Added the -boundary_depth option to icread_gds so the user can control the depth at which the translator will look for the GDS boundary. Default is one. Previously, translator looked at all levels. * Fixed problem with global router complaining about pins not being on a routing layer when in fact they are on a routing layer. * Major rewrite of the icnet command in the detail router. Now this command uses common code so it will be more reliable in the future. * Fixed misleading error message when global pins are not properly added to the design. Previous, it was stating no equivalent pins were found which is total bogus. Obviously, a copy and paste error. * Now support subcircuits at the end of SPICE files. * Row class constraints in the genrows topology program of the floorplanner is now persistent. Use the -persistent option of the icgenrows class constraint. * Added support and documentation for VALID_ORIENTS clause in fixed constraints. This will allow the user to set an individual instances valid orientation set. Previously, the set of valid orientations was set by the model. Now, one can override the model definition for individual instances. * Rewrote the Edit Row gui in the row topology generator of the floorplanners (ifp and igp) so that the class definition is persistent and alignment of supply pins considers layer. * Added save and restore capability for idetailer's cost structure. This file is called and .rcost file. These options have been added to the GUI. * Improved quality of the detailer router by eliminating some cases of slivering. In addition, improved code for aligning metal to vias which will reduce the number of DRCs for complicated routes. * Added missing iclayers command to first generation floorplanner ifp. Also added bin packing initialization code from igp to improve results. * Added a new variable pad placement algorithm based on dynamic programming which yields better results. Use *pad_new_algorithm : on in the .par file. In future releases this will be the default algorithm. * Added support for environment variable ICVERSIONCHAR which allows the user to specify the backup separator. This is needed for MS filesystems. * Rewrote icplacepads::beautify so that it is more effective. * Added support for virtual pads and ports. This was need to model Virtuoso pins more accurately. * Updated icgds find command so that it can work on a single gds layer. * Fixed problem with contracted netlists in the gridded router. * Fixed problem in the global router which erroneously assigned the positions of feedthru pins to off grid positions. The problem was in the vertical constraint minimization stage. * Updated LEF/DEF parsers so that they can read DOS file format. * Improved syntax algorithm so it does not exhibit O(n2) behavior on circuits with explicit power and ground representations. * Improved the icread_synopsys translator command so that long lines do not result in a syntax error. Now handle internal pins correctly during parsing. * Added gridding to the output_at_density option of the global router. In addition, we added the output_horizontal_layers option to control the number of horizontal layers used for the density calculation. * Improved pad placement code using linear assignment. Now both gridded and griddless router use the improved code. * Fixed problem with the icreplacement_policy keepouts replace in the translator. Previously this command had no effect. * Updated the icrecord command so that it support the -noexec switch and the -- options. The -noexec switch was needed to output the Tcl commands into the history when script generation routines are executed. * Improved the power/ground construction scripts in the detail router so that they now output the commands necessary to run the same operations in a do script. You will now find the commands in the Tcl history and .ddid file. * Added PAD_NEW_ALGORITHM option to the ncons files for convenience. * Fixed problems with removing overlap of cells in vertical rows. * Fixed problem with license server logging so that more exit points are supported with better error messages. * Fixed missing property attribute for wires in the CCT translator. * Now license server uses the /var/tmp/.itools directory to store the lock and pid files. This is to be compatible/consistent with FLEXLM and prevent cron jobs deleting these files accidently. Previously, the pid file was in /tmp. * Fixed a bad crash in the detail router due to new pad placement code. * Fixed a major problem in the placer specifically due to the cluster program. This bug was introduced in June in version pre35 when the attempt to "Fixed problem with infinite loop in clustering for some special netlists." was incorrectly implemented. Version pre35 is considered defective and should not be used for placement. * Fixed crash in router when some pins are incorrectly placed in the design. Now an error message is output. * Fixed a problem in the detail router's route generate code which was causing a crash. The tell tail sign was the router would output an error message denoting that a logic error was detected. Soon afterward, it would crash. This bug existed in all versions after version 2.0.0 pre34. * Now prBoundary is calculated with only the metal layers during a CCT translation. * Updated the compactor code so that core areas may have negative offsets. * Rewrote the class constraint code so the the default block class is 0 and not 1. This is much more easier to understand and allows the user to assign block class 1 to row 1, block class 2 to row 2, etc. making classes more straightforward. In addition, this is how this constraint was originally envisioned. * Added the icnet properties command so we can manipulate net properties in the translator. * Fixed problem with pad editor orientation bitmap. Orientation 5 referenced the wrong bitmap. * Added more support for power supply partitioning. Initial support for single row partitioning is finished. Optimization still needs work. * Added initial support for define statments in Synopsys .lib files. * Now support row pedestals correctly in the global router when adaptive spacing is enabled. * Now icread_verilog takes -module option so we can flatten the verilog in one Tcl command in the case of the top level module is not the last module occuring in the Verilog. In addition, the default flattening now stops when the flattener encounters a model which has a physical representation. Fixed problem with missing trireg keyword which was causing bogus syntax error reporting. * Added the icflatten_verilog apr_stop command so one can control the flattening on an instance basis. * Now -used_models works properly on the icwrite_ic command when hierarchical cells are present. Version 2.0.0 pre35 ======================================================================== * Added EZedit script to implement an interactive itools library manager. * Added icmodel ports Tcl command to output ports of a pin. * Added -Q (quiet) option for prettier startup output for EZedit. * Fixed crash in route_only case (igrouter) due to changes in internal graph structures. * Fixed channel compaction when one routing layer is much wider than any other layer. * Added initial support for itools interactive editor. * Added -popup option to icrouteable_report so popup can warn users when unrouteable nets exist. * Added itoolslm alias for EZedit. Added version cache to libmanager in EZedit. * Added filter options to the icgds enumerate command. Added MERGE ability to the icgds_define LAYER command. * Added the -ignore_bind_errors command the the icread_ckt and icread_ic commands. Added the icexit_on_bind_error command to handle bind errors in general in the translator. * Fixed bug in parallel placement algorithm which was degrading the results. * Update the parallel host creation and manipulation tool ichost so that it understands the icdaemon and uses it to test the parallel setup. * Improved the graphics behavior when in the parallel mode using icdaemon. Previously startup times were extremely slow. * Added support for clock spines. Now the placer runs twice to place clock drivers such that all loads are either in the same row as the driver or in either of the two adjacent rows. * We now turn off port compaction except for the last iteration when speed is set to fast 20 or greater so compaction doesn't dominate run time. * Added support for uniform sparecell placement. * Added the iccost relax_minjog command to the detail router to control minjog design rules. * Fixed typo which prevented reading ANTENNACELL in the LEF translator. * Added the ability to recognize instance placement properties to discover the instance name. Added the icgds property command. * Added support for extracting the prBoundary from CCT input files. * Added GRID_IOS to .ncons file. * Fixed problem with infinite loop in clustering for some special netlists. * Added power/ground mesh generation interface to the detail router. * Added driver centering constraint to the clock spine constraint. * Added ability for the user to supply the log file pathname. In addition, now we create the .itools directory if it doesn't exist so the default log file will work properly. * Improved error handling capability of LEF reader. Now complains when geometry supplied is in error. * Added the icgds_define SUBSTITUTE layerx WITH layery rule so user can modify GDS on the fly and replace the routing layer input to itools. * Now the placer does not spend excessive time in the final stage placement algorithm when fast placement is requested. * Added icrow given_boundary command in the iplacesc program. * Fixed problem with autodetecting placement scripts. * Added pre_equalize_row option to placer for completeness. * Added ability to allow_row_overlap in the global routers for completeness. This is a risky endeavour as the global routers assume that cells in the rows do not overlap and its use is discouraged. * Improved the IO routing appearance by routing each of the nets in a clockwise order starting from the bottom left pad. * Added pad routing optimization Tcl function for detail router. Added this function also to the place pads dialog box. * Fixed problem with pre_equalization of rows in the placer. Now spacer cells are properly added to the design. The global router performed the algorithm properly and this error is only seen if only placement is performed. * Fixed problem with small misalignment of layers in the detail router. * Added icvias grid_if_possible option in detail router. * Fixed problem with writing out SPARECELL constraints. Previously, there were no spaces between the keywords. * Fixed problems with floorplanner not reading the correct parameter file when performing detail routing. * Got rid of annoying warning message in detail router which states the tile is NULL. * Fixed problem with global nets not routing properly. Problem was that not all global pins were being added to the list of target route pins. * Now spine buffer are assigned using linear assignment so that row overflow is minimized. * Added the icspeed command it iplacesc. * Now we revert to left-edge standard cell placement when row pre-equalization constraints are badly specified. This way a good result with respect to wire length is returned. * Improved result when many spacer cells are present. * Added the icnet globalbind command. * Added missing Wire Length Monitor command to igp floorplanner. * Added the -pin_type option to rowstraps GUI. * Fixed problems with icglobal_nets function. Now output is correct whenever implicit global signals are requested. * Fixed problems with initial bin packing algorithm in the igp floorplanner. * Now core size is properly reinitialized when rerunning the floorplanner in igp. Now we calculate a minimum size for the core based on bin packing and we don't allow the automatic size of the core to go below it. * Fixed problem with output_at_density spacing in global router. * Fixed problem with searching EZ for keywords. Previously it complained that ...icsearch.js could not be loaded due to an unterminated string literal. * Now we make sure that all class assignments to clock spines are properly within the range of valid rows. In addition, centering option now works properly. * Now both icinstance core and icinstance corecell work properly. Some Tcl scripts were referencing icinstance corecell which wasn't implemented. * Added POWER_MESH constraint to .ncon constraint file. * Added icgds_label_instances_from_text option so we can extract instances from GDS when instances are labeled. * Added the icplacepads::assign function in itranslate so we can assign pads to sides if needed. Also added the icrow::assign function so we can extract row info from a placement. * Added ability to reference icmesh GUI capability from an idetailer script. * Fixed problems with stacked vias in contour detailer router. Now generated routes do not create massive design rule errors. * Fixed problems with extracting rows in translator when feeds are present. * Added the depth option to the icgds find command for completeness. Added icgds lookup command so we can get gds layer numbers from symbolic name. Also improved gds commands so that you can either use raw GDS units or design units. Added the -obey_cons and -verbose options to icpad findside command. * Added a tolerance option to the sparecell constraint. * Added the CLUSTER constraint for row-based placment. A cluster may be defined by the user by using the CLUSTER constraint in the .con file. See EZ for more details on the constraint syntax. * Began work on adding CLUSTER constraints to igp. * Added CLUSTER_SUBCIRCUIT constraint to .ncons file constraints. * Fixed problems with trying to fix undersized pins on cut layers in the detail router. This operation should only be applied to routing layers. * Fixed problem with false design rule errors when insulators are present in the routing. * Fixed problem with false design rule errors when insulators are present in the routing. * Added CLASS_EXPR, CLASS_MODEL, and ROW_CLASS constraints to .ncons file constraints. * Fixed problems with -setgrid option to idetailer placepads Tcl script. Now properly support padgroups in optimize pad routing command. * Added icroute_statistics namespace in the idetailer program so that we can make a routing report. * Added stdcell placement capability to the igp program. Now the second generation floorplanner can place stdcells as well. Version 2.0.0 pre34 ======================================================================== * New fat wire algorithm which is far more accurate in determining fat wires. * Fixed problem with global nets in the detail router. Previously, non global nets with the same name were being tagged as global. Now we correctly match by the group number. * Improved the neighborhood report file so that it now reports violations in decreasing order. * Added new algorithm to pre equalize the rows when in ECO mode. This is available in placement when ECO is in effect and equalize_rows is enabled in the parameter file. In the global router, this algorithm is enabled thru by either the enaabling of either eco_placement or pre_equalize_rows. In allow_space overlap mode, pre_equalize_rows is turned on by default. When the desired row topology is rectangular, this algorithm will generally achieve better results in the case of eco_placement or when space is allowed between cells in the row. * Fixed problem with buffering nets in "flat" placement mode. Previously, we only buffered nets in hierarchical mode. * Fixed problem with row topology program not outputting all rows. This occurred with some complex row topologies when rows were split with exceptions. * Improved the rigid neighbor algorithm so that it generates better results. * Unified the grid parameter option so the "grid xgrid xoffset ygrid yoffset" is valid as a parameter for all programs. * Now special width gets highest precedence followed by database width and then minimum design width for a layer. This allows one to route all nets on the layer above minimum design rule width in an efficient way. * Added ORIENT_MODEL, ROUTING_WIDTH, and TIMING_FACTOR to .ncons file. * Major rewrite of the path straightening algorithm in the gridless router. This was needed in order to satisfy notch design rules. * Added the -global, -noglobal, and the -index switches to the icinstance nets command. * Improved error checking for double row height cells. * Fixed problems turning off density display in global router. * Added support for inverse keepouts in the detail router. * Added minimum jog design rule checker in the detail router. * More improvements to detail router's path straightening code and added ability to visualize undersized pins. * Added eco_preview capability in the placer for user debugging. * Added the -e switch to the syntax program to enable more comprehensive syntax checking. The switch turns on keepout checking. * Updated the global router to handle stdcell macro obstructions properly. * Rewrote the supply alignment code so that it is not limited to a maximum number of geometries and now the power supply geometries are analyzed more carefully. In addition, a tolerance amount has been added to the parameter file call "alignment_tolerance". * Major rewrite of the detail routing to handle fat wires correctly. * New antenna rule design checking algorithm which is more accurate and very fast. * Improvements to the floorplanners pad placement capabilities. CORE and PADRING options are obeyed if possible. * Now allow both forms for icpad_ring and "icpad core" itranslate commands. Both commands accept both a list of coordinates or 4 separate coordinate arguments. * Updated the error messages in icinstance so they are less cryptic. * Added the ability to output representatives of each row class in the syntax program so debugging is easier. This is available using the "syntax -e -v" command line options. * Fixed problems with generating keepouts when using the icread_cct command in the translator. * Fixed a problem with the placer which prevented it from finding the optimal placement of a simple inverter chain. This problem resided in the orientation optimization code. * Added the ability to draw pedestals and references in the floorplanners. In addition, we added a crude compaction algorithm for use when user has specified the rows. * Rewrote antenna rule checker and antenna rule violation remover. The new algorithm is much more efficient. * Fixed problem in the detail router when reloading "contracted" netlist. Previously, global net indices were not updated after the contraction. * Added the ability to set the random seed from the command line. This feature was added to allow the create of the icexplore command which will run a set of placement and global routing steps and pick the best one. This is useful when you absolutely need the smallest die/block size. * Added the -lumped and -scale options to the icwrite_routing_sdf command. The -lumped command forces the command to calculate the delay as the lumped capacitance multiplied by the driver strength as opposed to the default Elmore delay of the routing. The -scale option allows the user to scale the result. * Fixed problem with channel compactor which prevented it from achieving maximum compaction. * Fixed problems with the iroute compacting algorithm when macro blocks are present. In addition, icregion_info minspace and extra space commands allow control over compaction constraints. Also fixed problem with origin of designs with macros. * Fixed problem of detail router dropping local connections to global signals. * Fixed crash of detail router due to a samenet via calculation bug. * Updated gds label routine so it puts the label in the center of the instance. * Added logging function to iclicensed so that exit reason is logged. Use iclicensed -bl or use the "license log on" from ladmin -a to enable logging. * Fixed vertical pedestals and vertical rows in placement. The overlap function was using the wrong dimension and so spacing was incorrect. * Added the icrow instances command in the translator so we can detect out of order cells. * Added the density_pad_adjust mechanism to the global router. Now there are two options when using this feature: move the pads or shrink the core when the adjusted cells just don't fit the given pad ring. * Added the EXPAND_PADS and ROWS options to the cons_options.tcl file so we can handle expanding the core using the density_pad_adjust feature and allow pre-existing row definitions in the .ncons file. * Added improved fat wire algorithm which speeds routing over previous fat wire algorithms. This is a major improvement over 34u and earlier versions. * Added more error checking to the SDF output routes function. * Fixed problems with icwrite_sdf function when writing lumped capacitance without including layout pin capacitance. Previous some pins were not output. * Fixed a crash in the detail router which occured when fat wires were *NOT* present. * Fixed problems with the design rule checking built into the detail router. Previously, it was misssing some fat wire errors. * New code to handle longer sets of inverter chains properly in P&R. If all inverter chains are placed in a single row, the probability of the placer finding optimal solutions has been significantly increased (100 out 100 runs). Version 2.0.0 pre33 ======================================================================== * Fixed typo which prevented drawing of ports in the translator when viewing in itools design mode. * Added overlap_algorithm parameter to the parameter file. This allows the user to control the overlap algorithm selection. The choices are best_fit and ordered. The ordered algorithm is necessary for the ECO flow. The best_fit algorithm was the original algorithm and it was intended for the gate_array design style. The default algorithm is best_fit for gate_array and ordered for standard cell design styles. The algorithm is only executed when rigidly fixed cells exist in the design. * Added the -append, -nocons, and the -fixed_xxx options to the icwrite_ic and icwrite_con commands. This allows scripts to filter output fixed constraints. * Added IO constraints processing to the icconstraints namespace in the translator. * Fixed a possible infinite loop in the generation of rows. Added support for vertical pedestals. Now we tell user when core-macro-rows option of icgenrows is in a state which would generate an unexpected row topology. Now icgenrows numrows command acts more sanely. * Rewrote compact_ports parameter to the track suffix so the spacing resembles the detail routing syntax which is easier to comprehend. * Improved the switch (options) placement algorithm when unconnected nets are present. * Fixed problem with instantiating griddless routing in the gridded router when a grid overflows with more than 3 nets at a grid. * Fixed problem with the generation of the path geometries in the contour router. Removes some minor notches. * Fixed problem with global router outputting pin groups which overlap. This creates unnecessary congestion. Now we automatically detect wired-or nets. The user has the option to allow or disallow the presence of cycles in these nets. * Fixed problem displaying solid ports and the mst connections in the itranslate design drawing program. * Added the -portwidth and -portheight options to the icportcells command in the translator. This now allows the user to control both the cell and port size of the automatically generated I/O cells. * Added right margins to some messages for prettier output. * Fixed Bugzilla #26 by rewriting directory structure of the floorplanners. In addition, fixed a major problem with the floorplanners. Both floorplanners ignored the output of the global router. Now both read the results of global routing properly. * Added initial support for reading CCT session files. Very rudimentary. * Added support for CORE_TO_PADSPACE and MINPADSPACE to the itranslate ::icconstraints module. * Added the ::icplacepads::reroute command so the user can reroute just the IO pads if desired. * Fixed problems with log files winding up in strange places due to conflicts in the user path. Paths that include "place" in the name were causing the log file to be put in an unexpected place. * Fixed problems with iclayers pitch command which was incorrectly using pattern vias in the simple pitch calculation. * Fixed problems with iclayers pitch command which was incorrectly using pattern vias in the simple pitch calculation. * When in ECO mode don't due H-tree net buffering unless requested. * Added the icmodel routing_partition command so we can mark the routing center for virtual routing and abstract generation. * The icremote_server command has been updated to register the output errmsgs so we can redirect them to the socket. * Fixed problems with updating hot keys when editing commands with more than one word. * Fixed problem with PRIORITY nets in the global routers. They were being processed in the incorrect order. * Fixed problem with unlap algorithm moving cells a long distance when rigidly placed cells are present. * Added ROUTING_PARTITION keyword to the model syntax so we know the routing abstraction partition line. Using this we can generate better abstractions. * Now we detect and warn the user when an icwait loop would be problematic. If no interpreter or remote server is available, we skip over the icwait command. * Fixed problem in global router when a COVER cell had pins far outside the bounding box of all other data. * Major enhancement to the global router to reduce number of tracks when rigidly placed feedthrus exist. If you have any rigidly placed cells in the row-based core, this version will give great advantage. * Added icposition screen command so we can implement the icpointer::warpto command. Added the icpointer namespace so that user can warp pointer to desired positions on screen. * Now support fake H-trees as a way to do balanced routing. Error checking is suppressed when a skew constraint of -1 is supplied. * Added icconstraints::extract_cover_cell_neighborhoods in order to generate neighborhood constraints. Added new icgeometry bloat and merge operations to support this Tcl. We also added a -minsize argument to control the size of the smallest neighborhood. * Fixed problems with icrow density function. * Added the INSULATOR and _ICGENERATE_ keywords to the .lib file syntax so we can support options better. Switches which are normally closed can be modeled as an INSULATOR which allow the router to connect to the proper terminals and still allows LVS to work properly. The _ICGENERATE_ keyword allows ports to be generated as routing in the output file. * Increased the number of possible defined vias between any two routing layers to 16 from 8. * Added icresistance_route_costs which convert resistance properties of vias and metal to costs. This necessitated the addition of the iclayers resistance and icvia resistance commands. * Added substition lists to icwrite_placement, icwrite_gds2, and icwrite_skil_placement functions to allow replacement of models in these routines. * Added the -mcr_include_origin option to the icgds_define BOUNDARY command so the MCR calculation is unambiguous. * Fixed problem with hierarchical placer entering into an infinite loop. This was caused by no clusterable cells in the netlist. Now the syntax program detects this possibility upstream so that the appropriate control is performed. * Restored copy up feature of the .pl1 file to the itoolsdata directory. This was made inoperable when the directory structure was change in pre30. * Now icdaemon commits suicide when the file icdaemon_suicide is present rather than when icdaemon is not present so we don't have trouble when NFS acts up. * Improved the error messages when a layer is out of bounds, that is, when a user supplied layer is invalid. * Added support to handle undersized pins once again in the gridless router. In addition, we now use a more thorough algorithm to check for undersized pins. * Fixed problem with placement annealing schedule when using hierarchical algorithm. Temperature schedule was getting set incorrectly for large designs. Added a feature for advanced uses to control the exact value of the timefactor. If timefactor is specified as a negative number it will be treated as an absolute number and directly modify the timing cost. Otherwise, the user supplied time factor is used as a scaling factor based on accumulated statistics as our paper states many years ago. * Fixed problem with the ladmin -sq command crashing on some machines. This was due to a coding mistake in the RPC code. Unfortunately, this bug is being circulated in the latest tirpc versions on the net. * Fixed problems with idle task update of the graphics when moving and picking cells. Now you can even scroll the screen during a cell move. * Added simple cell alignment tool to the idetailer GUI. * Added icdraw instance_detail so that user can control look of instance separators in the detail router. * Fixed crashes when SKEW constraints are present in the floorplanner's netlist. * Fixed problems with truncation of routes when using abstraction methodology. Now by default all nets are truncated. Previously, global nets were not truncated and this was causing shorts. * Fixed crash in global routers when feed resources are scarce during feed reassignment. * Added FEED_PERCENTAGE, PAD_TO_ROW_SPACING, and ROW_TILE_MAXIMIZE constraint options. * Added Ignore Global Routing check button for convenience to the Visual LVS checker. * Fixed problem with exact pads being moved in the detail router. Added the -override_exact switch so we can move exact pads if we like but the default is to maintain the position given. * Now iplacesc does not stop executing on error messages. It now tries to do as best as it can. * Now we support the ROW option to compact_ports so we can place option cells away from the rows. * Added output file support to itranslate GDS support. Fixed problems with dumping cells with dollar signs in their name (pcells). * Improved the icnet isolated command in the detail router so that all sets of pins are returned when the isolated pin is a set of pins. * Fixed design rule problem with diffnet spacing rules in the detail router. Bug # 20. * Fixed problems with routing going outside of the routing region. Bug #27. * Fixed problems with the icrestore -keepouts command. This command did not process fat wire rules properly. * Fixed problems with added a via placement in the GDS2. We were incorrectly adding an offset to the coordinates of the via placement. * Fixed problem with connecting to the correct position of a freeway during feed assignment in global router. * Now we report naming problems when performing special trunk routing of clock grids. Bug #15. * Fixed problems with placing vertical rows. This problem exists when option cells exist and/or only vertical rows exist. * Added support for RIGID_NEIGHBORHOOD constraints. These constraints require the instance to remain in the neighborhood and every effort is made to achieve the constraint. * Now properly restore net bounding boxes upon a restore in the detailer router. This was preventing some nets from being routed. * Reworked code to mininize fat wire rule design rule errors. More fixes will be applied to version pre34. * Rewrote SDF output code so that user has more output options to control the output. See icwrite_sdf_routes for info. * Fixed problems with output filtering of equivalent nets in the detail router. Previously, it was duplicating the output unnecessarily. * Improved the code for pin connection points when pins are undersized. Version 2.0.0 pre32 ======================================================================== * Fixed problem with notchfilling when using the gridded router (only the gridded router). Initialization problem was creating donuts. * Fixed problem with improperly displaying the program options of iroute. The -d and -do are two different switches and it was confusing to users. * Now we support a prerouting constraint file which contains the exact order of the prerouting pin locations. This is very useful in customizing the pin placement used in prerouting. If an entry is not found for a model, then prerouting reverts to original algorithm. * Fixed a problem with initialization of certain types of obstacles during detail routing. This problem could lead to design rule errors. * Fixed a problem with too many open file descriptors during translation. This was especially bad for CCT translation. Added a user controllable limit to the number of messages when nets cannot be bound. Version 2.0.0 pre31 ======================================================================== * Major rewrite of the detail router redraw code in order to speed up redraw times. Now manual editing of large designs is much less painful. * Fixed major placement problem for very large clock synthesized designs with timing constraints. Due to an off by one problem, the last stage result was being ignored and the initial state was being restored resulting in suboptimal placement. * Now we check to make sure spacing tables and wide wire spacing rules given by the user are consistent in the detail router. First attempt had some problems and now it is rectified. * Improved the EZ gds2 interface so one can read in a gds2 map file. * Improved EZ grand.do script generation. Updated for new tablelist version. * Added the -libname and -no_defs options to icwrite_gds2 for more output control of the GDS2 (itranslate program). In addition, we added the -only_referenced option so that only referenced cells are output into the GDS2. * Added the icboundary stdcell command for handling the core in mixed stdcell macro blocks in the detail router. * Improve redraw times for zoom functions. Now zoom functions respond immediately. * Fixed problems with crash of placer when no nets are given. * Fixed major problem with prerouting cells. Ports that spanned multiple columns were not being handled properly. Now such cells are prerouted correctly. * Added clock grid for paranoid clock tree distribution. This method has extremely low clock skew at the cost of a bit more routing. The placer now outputs the itools.ckt file whenever clock trees are present as it should. * Fixed problem with translator using tremendously large amounts of memory when reading in a routing. * Added core abstraction for final step of routing to ease time and memory requirements. * Added trunk routing support to the gridded router. In addition, the contour router now supports both trunk and trunk only options. * Fixed parsing problem with icread_cct command. It didn't understand rotated vias in the image file. * Fixed problem with contour router outputting a unconnected net. The router did later connect the net but with a minimum area mistake due to the underlying path generation problem. * Added paranoid via processing to make cleaner routing in the contour router when "fat" wire rules are present. * Added abut attribute to begin support of pins which are routed by abutment. * Added support for PEDESTAL constraints in the row definitions so users can define alignment positions. Also updated row_adaption to handle rows aligned by offset properly. * Now report when 0 nets are present in the design. * Fixed overflow problem in the placer when design is immense. * Fixed problems with ripup and reroute in the gridless router. The algorithm was not effective as it should have been because of a typo. * Fixed problem with routeability analysis in that some nets were marked unrouteable even though they were routeable. * Fixed problem with global router not correctly connecting abutting pins properly when macro cells are present. * Fixed crash in visual design rule checker when notchfill rule is violated with an obstacle. * Began work on a verification option in the iroute control program so we can verify routed designs in the detail router. * Fixed crash in icread_cct command when keepouts occur in the structure section. * Fixed problem in the command icgds enumerate routine which was erroneously returning the wrong data. * Updated syntax program to output class offset info into the .stat file so that we can support pedestals properly. * Fixed problem with the icfile_build only option in iroute. Now when it appears in the .rdo file, the input files for the detail router will be built without executing the router itself. * Now feedthrus are drawn orange so we can see DRC violations better. * Fixed problem with virtual keepins which in some cases generates DRC violations in the row routing. * Added the -e switch to iflow so that errors can be display in graphics even if -nographics was issued. * Added more options to the itranslate command "icreorigin" so it is more flexible. * Fixed CCT translation problems with via constraints in image files. * Improved the row exception capability in the floorplanner. In addition, we now properly construct row configurations when given a target number of rows and macros are present. * Fixed problem with wide wire spacing rules when unconnected pins are wide wires. Now we process unconnected pins so that they make wide wire keepouts. * Now when require vias is off in the parameter file, via errors are reported as warnings so that we don't prematurely kill a placement only run. * Improved the visual DRC checker so we can turn of highlight display. * Improved wide wire processing and added the "icrouter fat_wire" command to control the wide wire processing. In addition, we now align vias over pins so that we can avoid creating notches. * Added missing run time stats to the detail routing control program and now always give the runtime stats in the detail router at the end of execution. Version 2.0.0 pre30 ======================================================================== * Fixed problem with variable pad placement when core is offset from zero. Previously, code assumed zero and this is a problem when the core is not zero. * Fixed problems with -multi_cell_row mode at the entire step. The detail router was not adding the proper pins to the database resulting in unconnected routes. * Fixed problem with cutting out geometries with the icgrid punchout command. Now the command no longer processes global signal pins, ie. power/ground ports. * Fixed problems with assigning the synthesized flag when reading in the routing (.rte) file. Now all added spare cells are marked as synthesized if they weren't originally in the netlist. This was necessary to fix a problem when writing out the Skil placement code. Version 2.0.0 pre30 ======================================================================== * Fixed problem with translate omitting required covered cells. * Now the icconstraints module automatically sets the global pin type from the global net definitions. * Model the core cell macro in floorplanning much more accurately when the user knows how many rows of stdcells that they want. * Added the "iccompact_channel -simplify" to save memory during gridded region routing. * Fixed crash in translator when pin attributes were present in prerouting. We added the icpin attributes command which is used in the preroute.tcl module. Also fixed a crash when models are freed. Improved error reporting in the translator. * Fixed problem with the 64 bit version of the license server which was crashing in translating the network address. * Improved ripup and reroute code for both gridded and non gridded routers. Fixed problems with determining virtual grid when row height was uneven. * Fixed problems with multiple global pin definitions mapped to the same global name. Previously, we were only matching the first one found. This caused problems when performing power and ground routing. The detail router was reporting shorts where there wasn't a problem. * Now iroute can use the miscellaneous Tcl library. It is useful to grid the instances. Now iroute can grid the results if a grid is defined using the icgrid command. * Fixed problems with the flow.onlyroute1 flow. Now global router reads a top level .pl1 file if is supplied. This flow was broken by the new directory structure. * Added more messages to the iclicense -dv option. Now the license server tells which license file it is reading. * Added COREAREA and NUMROWS processing to iccons_options module. * Fixed offset problem with extracting prerouting in the translator. * Added the optional _ICSYNTH_ statement to the MODEL syntax so to be consistent with instance data and to allow recognition of itools created models. * Added ROW info to the .rte file so we can translate row position properly when the -multi_cell_rows option is in effect. * Added the -sorted option to icwrite_placement translator command so output will be sorted by row then left to right. * Fixed problem with misalignment of rows in the output of the detail router by now explicitly outputting ROW statements in the .rte file. * Fixed problem with poor placement results for large designs (10k objects or better). This problem was accidently introduced in version 2.0.0 pre 29 when buffer code was modified. * Added new feature in the global router to add spare cells to the design when equalizing row lengths. * Added adaptive row spacing to the global router for completeness. It is recommended to do adaptive row spacing in the placer but this allows flexibility. Version 2.0.0 pre29 ======================================================================== * Added ability to flatten and edit gds text labels. More options will be added over time so one can modify any aspect of the GDS2. In addition, we added the filter and id options to the icgds find command. * Added the icmodel pinattribute command so we can modify pin attributes in the translator. * Fixed problem with install pager directions which was introduced in version 2.0.0 pre27. * Fixed two long standing problems in the second generation global router igrouter. First was error reporting path is outside region. Second was the router could not find its targets. * Fixed crash in detail router due to bug in the ripup and reroute code. This was occuring in a very deep ripup in the gridless router. * Added SPLIT_ROW constraints and the icexcept command to the floorplanners to make row blockages easier to enter. * Now prerouting extraction doesn't add a conflicting fixed constraint but uses the one supplied by the user. * Now the icfix_instance get command returns the proper form. * Fixed crash in global router due to mistake in except process code. * Added parallel remote start daemons so parallel execution does not suffer from startup delays associated with rsh/ssh connections. * Fixed problem with multiple redraws during resizing of window. Now we redraw design only once. * Fixed problem with translating gds2 with extended polygon figures. The memory was not allocated properly. * Now we add vias to the output gds2 as placements rather than flag geometry by default. You can still add it flat if you desire with the -flatten_vias option to icwrite_gds2. In addition, you can also specify that vias are created in the gds2 from the definition in the parameter file by using the -create_vias option. * Rewrote width verification code so it uses less memory and uses a faster algorithm. * Added the -strict option to the icvirtual_keepin command of the detail router. This switch insures that region division is exact and no pin cutouts are performed except for vertical pins inside the region demarcation. * Fixed problems with reading macro spacing rules in LEF. * Fixed problems with sequential timing data failing with scalar setup times in the floorplanner. * Fixed short and wide wire spacing design rules in detail router. Some wide wire errors may still occur in the gridless router and will be fixed in next rev. * Fixed problem with duplicate menu command in igp.tcl. * Fixed ictell_tile function in idetailer. Now it returns the proper tile when draw contours is enabled. * Fixed problem with crash in placer when net exceeds 32K pins. In addition, we added the large_net_threshold option to the parameter file so we can control large net processing. * Added the icgrid instances function to the detail router to in order to insure that regions are gridded. Version 2.0.0 pre28 ======================================================================== * Implemented a new idetailer Tcl command "icnet type" which returns one of {signal power ground special} so we can improve the row strapping command. * Major rewrite of the floorplanners to handle mixed macro/standard cell cases better. Floorplanner global router will expand soft pins into real pins which can be routed. * Fix of a major problem in the second generation floorplanner igp. Cells were jumping out of the core area due to a logic mistake. Now we get much better floorplanning results. * Improved the speed of the contour maze router also known as the gridless router. * Improved the ripup and reroute capability of the detail router by relaxing via constraints. The relative via costs are preserved but the absolute value of the cost is relaxed in order to complete the routing. The new algorithm can be turned off using iccost relax off if desired. * Fixed iroute's compactor so that it properly recognizes the macros of a mixed macro/standard cell design. This program is now also more tolerant of bad density data. * Improved the parallel processing code for the iroute program. * Added the icroute_cleanup Tcl procedure for convenience. * Fixed a problem with the gridded detail router which was causing design rule violation in the top level including the mult_test test case. * Modified the buffer synthesize to fix problems with building H-trees when macro cells are present. Version 2.0.0 pre27 ======================================================================== * Fixed initialization problem with instances which was causing errors in translation related to fixed cells. * Fixed problems with selecting cells for editing in the placer. * Now we put "bad_net" output messages under user control so we can limit them. * Fixed problem with DEFAULT vias with multiple cuts being translated into a PATTERN via. * Now prerouting in DEF file is assumed as FIXED rather than CAN_BE_RIPPED_UP. We added the -routed_as_ripup and -routed_as_fixed switches. In addition, fixed problems with itools language always choosing CAN_BE_RIPPED_UP. * Added the -squareplus option to interpret DEF routing as centerline square plus (GDS2) instead of the default square flush interpretation. Added initial support for ctgen file parsing. * Now detail router tells when it is entering a wait loop. This helps when user has misconfigured the Tcl. * Fixed problems with parallel routing going into an infinite loop. In addition, we fixed a problem with the 1 license for any number of processors. This problem was in the license server so if you want to use parallel routing using only one license, you will need to restart the license server so to use this version and new servers. In addition, we added Expect support to the parallel algorithm so you can even use telnet to log onto remote nodes. This allows total customization of the parallel process. * Now prevent an infinite loop in detail router. * Changed flows and floorplanner programs so that the floorplanners call the simplify program internally in order to complete the versioning ability of all programs. * Fixed problems with icrow spacing command. Now if expansion would intersect the keepins, the keepins are deleted instead of wiping out the instance data. * Fixed problem with EZ search. Previously, EZ search did not work properly with 2 word searchs. In fact, EZ search was not implemented correctly and only one of its four modes was even implemented when Gordon wrote it. Now all four modes are implemented and exact has been renamed to glob-like to be more informative. * Fixed problems with alert boxes in the graphics programs. For example, iplacesc would not respond to reporting its version due to an initialization problem. * Fixed problems with scaling parameters if the RULES section occured in the .lib rather than the .par file. First noticed in igp where core was scaled improperly. * Fixed problem with adaptive row separation algorithm when in gate array mode. * Now the default routing bounding box of a net in the contour detailed router is +-15 track pitches similar to the gridded router. This speeds up routing tremendously. * Fixed problem in the prerouter which prevented the proper completion of the routing. It was due to picking the largest via for a constraint instead of the smallest via. In addition, we added icpreroute_status so the prerouting log file shows the number of unconnected nets and number of design rule errors after prerouting. * Updated warning message for power/ground pin row alignment code. In addition, we now support multiple port geometries properly. * Added support for forbidden placement intervals. * Rewrote over the cell feed thru assignment code so that upper layer feed thrus may be assigned more efficiently. * Improved the scanpath discovery code to issue better warnings and messages when errors occur. * The itranslate icshort code now merges prerouting properly. In addition, it has been updated to handle names surrounded by {}. * Fixed problems with asymmetrical via. Code was rewritten so that it makes better use of routing area and does not create design rule errors. Also improve icrestore -database command when using gridded router. * Now icpickbox updates the coordinates of the second point during rubberbanding. * Fixed problems with poor routing when row gravity is enabled. * Now install program warns about installing 32 bit version of Linux on a 64 bit machine. * Reimplemented rubberbanding graphics to use blitting rather than the archaic XOR method. * Added the iccritical noripup command to the detail router so we can allow the user to keep critically routed nets. * Fixed problem with crash when aligning cells with power/ground rails when standard cells are large and have many power and ground ports. Version 2.0.0 pre26 ======================================================================== * Updated iplace program to use new flow graphics. * Fixed problem in global router which was causing a crash when cell instances were added in the .gdo file. * Added width optimization flow named flow.widthopt1. This flow will iterate until the width of the design matches the target. Width optimization can be controlled with three parameters in the .par file ICSC*width_optimize : ICSC*max_numrows : integer ICSC*width_tolerance : [0 .. 1.0] The first parameter is mandatory if you want to perform width optimization. If width_optimize is missing, then you get the conventional flow. The other two are optional and have defaults of 1000 rows and 10 percent tolerance or 0.1. Of course, you must have the flow set to flow.widthopt1 * Now icpar_option returns the current value of the option when only 3 arguments are given. * Added missing pad options to detail router include contiguous pad option. * Improved variable pad placing algorithm so that wire length is reduced and wires are straighter. In addition, fixed problems with pad permutation algorithm so it now works. * Fixed a crash that occurred in the fast router when routing global signals. * Fixed problem with DEF reader. It had a typo with SPECIALNETS and was missing support for FOLLOWPIN which has now been added. Version 2.0.0 pre25 ======================================================================== * Major rewrite of the iflow program so that it now supports decision objects. By using Expect in the decision object one can now build iterative flows easily. A preliminary flow editor is supplied as well. This program rewrite was necessary to allow width optimization thru iteration. Now it is possible to automatically optimize the width of a row-based design without manually knowing the number of rows necessary apriori. The new program also has a new look. * Now we generate PDF documentation from EZ. The new generation tool is under the Tools menu. * We now include the expect library so we can write expect scripts in itools for more capabilities on starting remote programs. * Now we give better error messages when GDS2 structure name is too long and rename it to XXX#. * Fixed and enhanced ability to handle stipple patterns in the global and detail routing programs. * Added support for DIFFNET spacing rules for via layers. Added the "icrouter via_obs_are_wires" command so that we work around LEF ambiguities. The default setting is off which means via obstacles definitions in LEF are treated as keepouts for any diffnet rule. If you need them to be wires either via_obs_are_wire command or better yet use the VIA_OBS_ARE_WIRES in the design rules which was added just for this purpose. * Added -pin_align option to prerouting so we can position pins in alignment with a specified layer. This is useful when stack vias are possible and the cells are very complicated. * Updated the Commands Help display so that it properly displays all commands in ::icxxx namespaces and now sorts them so you can find commands easier. * Added the LVS visual connectivity checker for helping show unconnected nets. * Added edit cell dialog gui in iroute for convenience. Also updated iroute so that it properly called the Tcl initialization functions. * Added icpad command to idetailer so we can modify the pad placement more completely and easily using pad constraints. We also added pad gui editing items to the EDIT subment. * Modified RELATIVE pad syntax so that both RELATIVE and RELATIVE statements are understood. The second form allows quick conversion from EXACT constraints to RELATIVE constraints by the change of the keyword and is added for convienence. * Changed the default row to tile spacing in the row topology program to 0 from 1 as this makes more sense. The value 1 was arbitrary and causes problems with gridding rows properly. * Implemented a graphics timeout so that slow network connections don't generate the error: ERROR[ICinitGraphics]:Cannot find window for symbolic name:.frame5.frame7.frame1.canvas2 ERROR[initgraphics]:Aborting graphics. Instead we wait for a specified amount of time before generating this error. The default is two minutes but can be set with the itools*timeout option to the .Xdefault file. * Many documentation updates. * Updated the graphics dump command. Version 2.0.0 pre24 ======================================================================== * Fixed problems with LVS problems during entire route. Removed some confusing error messages during gridded routing. * Fixed problem with icrouteable command when using the gridded router. Previously, it was chosen the incorrect routing source so output was in error. * Fixed problem with reading old .rte file formats which did not use the new GROUP keyword. * Fixed problem with global router which was allowing access to both sides even though access was blocked on one side by a keepout. * Now allow core_to_padspace to support the 't' suffix so the user can specify the distance in tracks. Updated EZ so the regions.ddo file can make use of this feature so that pads are not too close during region routing. * Added output message control to the stripes and ring power and ground GUIs in idetailer and EZ. Fixed problems with missing strap dialog in EZ. This was creating a message that the primary layer was not set. * Fixed problem with pad placement when gridding option was set. Now the core is adjusted to the proper size. * Fixed a problem where floorplanner was stuck in graphics wait loop in a non graphics mode causing an infinite loop. Version 2.0.0 pre23 ======================================================================== * Added -ycenter option to the icpreroute command so we can support y-asymmetrical libraries for prerouting. Also now support prerouting with partially assigned pins (pins on the correct vertical layer). * Added gridded router support for the icrestore -instances command. * Added support for multiple grid vias when using the gridded router. * Fixed problem with cells disappearing during redraw when in zoom. * Fixed problems with Postscript printing of design. The upgrade to a newer version of Tcl/Tk was incompatible with previous output method. * Fixed problem with MINAREA rule rounding during translation. Not enough significant decimal places were being output. * Fixed problem with prerouting process output having extra copy of via information. * Fixed problem with igrouter outputting the wrong placement. It was outputting the initial placement and not the adjusted placement. * Improved the printing GUI for printing scaled regions. * Now avoid crashing in the detail router when a pin is described by only non-routing layers. * Fixed major problem in reading parameter files in EZ. The tyacc parser was in error and preventing the correct reading of the paramter file. This resulting in written parameter file devoid of design rules. In addition, we now keep multiple backup copies ala VMS. We also implemented tainting so that we only change the update color to red now when the user actually changes a value. * Improved the EZ startup when specifying a project file. Now the command EZ works with both full and partial pathnames. * EZ now supports reading of the design log file under the Tools Menu. * Improved the power ring gui in the detail router. Now we allow the user to select message mode. * Changed the backup file separator from . to : so file name will be more readily apparent. * Added initial support for minimum enclosed area design rule. * Now we model the world pin of a ICPORTXXXX cell as a logical pin so we don't create a conflict in the physical domain. * Added support for RESERVED_LAYERS which allows the user to avoid using a layer or set of layers in placement and router even though the layers are defined as routing layers. * Fixed problem with missing prerouting when the -multi_cell_rows option is in use. * Fixed gds2 write problem which placed all of the cells on top of one another when using the SunOS5-m64 OS. Version 2.0.0 pre22 ======================================================================== * Fixed crash when SITEDEF data is present in constraint file. * Fixed problem with categorizing the last net (alphabetically) in the design as a bad net. This occured during reading the constraints and was due to the new global routing format parser. * Fixed problems with reading routing into translator for final output. * Fixed problem with fast router so it works with spacing tables. Version 2.0.0 pre21 ======================================================================== * Major rewrite of the data structures in order to save memory in the detail router. We still have one more stage of reduction to come. * Added the icrouter logmode and the -silent option to the reroute and delete net commands to minimize I/O load during routing in graphics mode. * Added cells_may_abut feature so that we can abut macros and not require spacing between them. * Improved ripup and reroute capability in the contour router. * Now we save the best result found in the second generation floorplanner and return it as the final solution. * Fixed problem with backslashed Verilog port names. Began work on fixing memory leaks. This version is for Mondowave. * Now detail router works in parallel mode with just one license. We added license_max_tries option to iroute to facillitate this feature. * Now we support N and P implant layer types. * Fixed problems with GDS2 processing creating off manufacturing grid keepout data when adaptive stairstep is on in itranslate. * Added -max_area flag to prerouting algorithm. Added the -open_fail_ok option to the iccreate_abstractions command in itranslate. * Added the -process_only switch to icread_gds2 so we can read all GDS2 in first and then perform processing. Version 2.0.0 pre20 ======================================================================== * Fixed problem with crash in placement program when double height cells are present and the row spacing is nonzero. Updated the floorplanner so that doubleback rows work properly. Version 2.0.0 pre19 ======================================================================== * Fixed problem with crash in cluster program. This crash occurred when the target number of cells per cluster was calculated to be less than 1. Now the target number of cells per cluster is limited to 1.0 Version 2.0.0 pre18 ======================================================================== * Added the ICGR*pre_equalize_rows function so one can equalize the row lengths in global routing when special constraints are present. Normally, this isn't required. This code replaces a Tcl script. Version 2.0.0 pre17 ======================================================================== * Updated icread_synopsys function to parse wire_load_table_option properly. * Added the -timescale option to the icwrite_routing_sdf command. Updated so that arrayed net names are properly output in icwrite_spice_parasitics and displayed in the common nets dialog box. * Fixed problems with double height core dump when fixed constraints are present. Version 2.0.0 pre16 ======================================================================== * Fixed problems with doubleback row generation. Previously, it was failing with the error: ERROR[readblock]:block height is less than 1 for row:2 at (5 19.850) (201.204 19.850) Must exit. * Fixed ring and stripe FROM CORE and FROM IO equations so that spacing is correct. In addition, updated placepads.tcl so the interface is cleaner and able to support core to pad spacing on a per side basis. Version 2.0.0 pre15 ======================================================================== * Fixed design rule and unconnected net problems in gridded router. The unconnected routes were due to an error in the ripup mechanism. Added a new mechanism which can handle complex via rules. * Fixed spacing problem in region compactor when no routing was present. This was causing channel to collapse to zero even though there was a row spacing constraint. We also update the channel compactor to penalize removing tiny slivers one at a time. * Added the missing rules : icrule add WIDTH and icrule SPACING ... STACKDIST commands to itranslate. Also added icvias add_no_geom in order to create PSEUDO vias. Also added icrules add OVERHANG rule and icrules add MINAREA rules. Added dummy filter to translator to remove all dummy instances for testings sake. * Added better error check in EDIF translation. * Fixed draw layer GUI to be correct y size. * Updated translation of Magic files and now translate technology file. Began work on multilayer (>= 3 layers) vias with the addition of PSUEDO vias which can have any number of layers. Currently, they are only used in translation. Future versions will have true multilayer viass. * The detail router now supports a manufacturing grid of 1 needed for support of Magic designs. * Added the -model_obs option to icread_gds2 and icread_magic for completeness. * Fixed problem with global routers moving cells to different rows during row equalization (feed padding). * Fixed problem reported by Silicide ApS where the global router was allowing a rotation of a cell to an illegal orientation. This was occuring in vertical constraint minimization. * Fixed a problem in the virtual keepin code which was not allowing a via connection in the gridded router. * Preliminary support for Sparc 64 bit architecture (v9). This is compiled -O using gcc 3.4.1. Unfortunately, higher optimization levels are unstable due to gcc bugs. Will migrate to Sun 64 bit compiler in the future. Version 2.0.0 pre14 ======================================================================== * Fixed problem with placement gate array mode where cells were being placed outside the left end of the row when the defined row was less than the sum of the total cell width. Now the code automatically relaxes the row length so all of the cells can fit with 85% utilization *OR* the program exits immediately if the new option gate_array_exit is enabled. * Improved the overlap removal code for double height cells in gate array mode. * Fixed problems with removing row length due to feed thru length estimation when conserve row length is off. * Added a new WEB-based registration method in EZ to augment email registration. Version 2.0.0 pre13 ======================================================================== * Fixed problem with icrule add spacing range command. Needed for row spacing. * Added missing DRC check for samenet and via cut obstacle rules in the gridded router. * Fixed problem with the status command returning nets are unconnected when they are connected. This affected equivalent pins in the gridded router only. * Added pattern row separation feature in ifp so once can make a repeating spacing pattern. * Rewrote the magic via translation code for input/output. * Fixed problem with buffer tree synthesis. In some cases, it was reporting ERROR[TWfixcons_init]:block assigned to instance (block 0) is out of range as specified in the constraint file - (# rows = 275) * Added EZ documentation for minimum row-row spacing and illegal spacings for row separations. In addition, we updated the detail router algorithm so that the code will work more efficiently. * Fixed problem with vectored signals in EDIF translation. Version 2.0.0 pre12 ======================================================================== * Fixed problem with LEF translation with modeling obstructions as wires. Added the -remove_port_obs switch to icread_lef so we can support LEF 5.5 port access rule that a pin is accessible is port is less than minimum width + minimum spacing to the edge of obstruction. Some abstract generators generate LEF with this requirement. Updated EZ documentation. * Added the icrule add SPACING STACK command to support via stacking rules for different nets (not samenets). * Added steiner tree wire lengths to .gpth report file. Version 2.0.0 pre11 ======================================================================== * Now we don't write internal spacer cells out to the itools.ckt file. * Now by default, the translator creates a feedthru with as many vertical layers as possible so we have good routing density. * Fixed problem with icinstance exist function returning a message instead of just a Boolean. Applies to all programs as this is in the common Tcl module. * Fixed problems with dumping spacer cells into the itools.ckt file. They should not be present in the netlist. * Finished rewrite of placement code for double height cells. Now row-based placer reports cost after legalization so that cost output is now the legal cost rather than the lower bound on cost. Previously, it was confusing to user. In addition, we now capture the lower cost solution found and restore it at the end if it is lower cost than the final cost. This is very useful for small designs (under 1000 placeable objects). * Updated SOFTGROUPS to work with double height cells. * Added ignore_non_routing to save memory in detail router. * Rewrote icscan discover command to make scan path work for non flip-flop end points. Will change spec of scanpath in a later revision in order to make data checking easier. * Fixed a bug in the notch filling algorithm which was causing crashes. Version 2.0.0 pre10 ======================================================================== * *BEWARE* this version has a bug in the output section of the detail router which causes a crash. This version is only useful for testing. * Completed and tested the code to implement double height cells when using allow_space mode. Work was begun to handle multiple core regions. Currently multiple core regions only work with row exceptions. * Added LENGTHTHRESHOLD to the detail router. Internally, this was implemented using spacing tables. In the next releases, we will make spacing tables available as user input. * Fixed a problem with stacked vias being all located on top of one another. Version 2.0.0 pre9 ======================================================================== * Fixed a very bad bug in feed_obstacles which was causing crashes in both globals routers. This bug was introduced in 2.0.0 pre 5. * Fixed problem in bgexec command which crashed EZ when the command redirected output files. Sent patch to sourceforge. * Added bendcost_threshold documentation to EZ. Version 2.0.0 pre8 ======================================================================== * Fixed problem in syntax program when cover cell does not have a boundary. * Added the TKPLACMENT="before" option to JS_COND statement in EZ to make HMTL documentation writing easier. * Added the autodetect_script option to iroute so program looks for design.rdo file automatically. Also added to placer (design.pdo), floorplanners (design.fdo) and global routers (design.gdo) * Fixed problems with GDS2 and LEFDEF viewer when filename in form was blank in EZ. * Improved routing HTML in EZ. Hopefully, it will less confusing. * Fixed some problems with sending data to InternetCAD.com in in EZ. Some still remain. This is a bug in the Tcl core. Will fix in the next release. * Fixed ifp so it writes the rules properly for its floorplanner. This was missing code as the second generation floorplanner igp was coded correctly. * Enhanced the first and second generation floorplan compactors so that they relax the core constraints in order to achieve a solution. This prevents an overlapping solution from occuring. * Added the require_via option to the global routers so that vias are not required iff detail routing is not required. * Added ability to generate boundaries from sizer rules in the translator. Added the -nosubstitute option to the icgds_def_rule itranslate command. Added the MCR operation to the sizer to support automatic extraction of boundaries. * Fixed problem with properly extracting the I/O pins from an EDIF netlist. Added check to see if we have a case problem when binding ports of an EDIF netlist. * Added the -merge_layers option to the LEF reader. * Added ez:write_design_rule_commands so we can generate a script to generate the design rules. A good teaching exercise. * Fixed problem with creating a portcell with totally bogus size (nan) when the manufacturing grid wasn't specified. * Added the flow.iplace2 flow which is a second generation placement only flow. * Fixed problems with reporting errors in both first and second generation global routers when the pin is a point. This occurs in the standard cell tutorials. * Added bendcost_threshold option to the placers : igp, ifp, iplacesc, and iplacega. This allows the user to trade off wire length for wire alignment. * Fixed an initialization problem in the second generation floorplanner. This was causing an infinite loop. Version 2.0.0 pre7 ======================================================================== * Fixed problems with clock tree synthesis when synthesizing 5 or more levels of buffers. Version 2.0.0 pre6 ======================================================================== * Fixed DEF translator to properly handle REGION definitions. * The contour (gridless) detail router now supports different spacing and width in x and y direction. This allows poly to be fatter in x than in y. * Fixed a problem in the DEF reader when reading asterisk points for a rectangle. * Added icscanpath command to translator so that it is easy to discover scanpaths in the netlist. * Fixed problems with license server FIREWALL command. Previously, squid proxies were not working properly. Version 2.0.0 pre5 ======================================================================== * Updated both global routers so that obstacles on the feed thru layers are taken into account when assigning feedthrus. * Now buffer tree may have any depth if the state is assigned. If the state is not assigned, the depth is limited to 4. * Fixed problems with Synopsys library support. Quoted strings and the define statement were in error. * Fixed problem with virtual pin assignment in the detail router. This was due to a mistake in the cut line calculation used in region routing. * Added better status message when EZ is waiting for a process to finish. Version 2.0.0 pre1 - pre4 ======================================================================== * Updated support for MacOSX Panther. Jaguar is no longer supported. * Added new icmodel subcommands: pin_exists, gate_area, diffusion_area, pgate_area, and pdiffusion_area to allow programming of antenna constraints. * Added library support for GATE_AREA and DIFFUSION_AREA constructs to support better antenna rule checking. * Added new port alternatives feature. * Fixed gridding problem when no manufacturing grid is present. * Fixed problem in accidentally using cover cell to build obstructions. If you use cover cells, you will get much better results. * Added the dreaded net weighting constraints to the constraint file. At InternetCAD, we really don't like net weight constraints but people were clamoring for them. Beware. See our DAC paper for the reasons. * Fixed problems with overlap removal code when allow_space is enabled. In some instances, cell overlaps were not resolved. * Fixed the second generation global router path straightening code for non OTC routing. Now all routes are in their proper region. Still to do : add minimum perturbation algorithm. * Added -remove_overlapping_keepouts option to the icmodel simplify command so that keepouts over pins can be removed easily. * EZ has been updated to handle power/ground meshes. * EZ now has lock-down feature so that use cannot change page during program execution. Changing the page during execution was destroying the integrity of the design flow. * EZ translation now asks questions about the supplied feedthru cell and the extraction of pad constraints. * Global router can now equalize the row lengths when rigidly place cells exist. * Fixed a problem with symmetrical detail routing which caused vias to disappear. * Now iroute draws the routing by default. Previously, user had to use the GUI to turn it on. * Updated the icinstance set command so that it conforms with the syntax of the constraint file. * Fixed problem with the translator crashing when using adaptive stairstep when reading in GDS2. * Fixed problem with incorrect output of routing into .scon file. Data was missing spaces. * Fixed problem with autoflow program which was not executing programs when the mandatory switch was enabled and more than one program was specified as a stop program. * Preliminary support for double height cells (placement only currently) * Improved support for Magic input files using a Tcl technology file. * Improved behaviour of pad placing code in detail routing when variable pads are requested. * Now the icstripe Tcl code may be issued in the detail router when in nographics mode. Version 1.4.0b250 ======================================================================== * Completely rewrote Steiner tree algorithm for the second generation global router. Now the global router and the detail router use the same A* algorithm so that the global router will predict the behavior of the detail router much more closely (besides being a much better algorithm than was originally coded). Now all routes should be connected and variable die spacing of macro cells insures at least minimum required spacing. Still to do: fix path straightening algorithm for non-OTC case and add minimum perturbation so wire length is optimized during spacing. * Support for first generation global routing scripts enhanced to enable the placement of power/ground strap cells. * Translator now supports LEF MANUFACTURINGGRID keyword properly.